mirror of http://shamusworld.gotdns.org/git/rmac
481 lines
9.2 KiB
C
481 lines
9.2 KiB
C
//
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// RMAC - Renamed Macro Assembler for all Atari computers
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// EAGEN0.C - Effective Address Code Generation
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// Generated Code for eaN (Included twice by "eagen.c")
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// Copyright (C) 199x Landon Dyer, 2011-2021 Reboot and Friends
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// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
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// Source utilised with the kind permission of Landon Dyer
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//
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int eaNgen(WORD siz)
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{
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uint32_t v = (uint32_t)aNexval;
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WORD w = (WORD)(aNexattr & DEFINED);
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WORD tdb = (WORD)(aNexattr & TDB);
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uint32_t vbd = (uint32_t)aNbdexval;
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WORD wbd = (WORD)(aNbdexattr & DEFINED);
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WORD tdbbd = (WORD)(aNbdexattr & TDB);
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uint8_t extDbl[12];
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switch (amN)
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{
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// "Do nothing" - they're in the opword
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case DREG:
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case AREG:
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case AIND:
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case APOSTINC:
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case APREDEC:
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case AM_USP:
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case AM_CCR:
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case AM_SR:
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case AM_NONE:
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// This is a performance hit, though
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break;
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case ADISP:
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// expr(An)
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if (w)
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{
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// Just deposit it
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if (tdb)
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MarkRelocatable(cursect, sloc, tdb, MWORD, NULL);
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if ((v == 0) && CHECK_OPTS(OPT_OUTER_DISP) && !movep)
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{
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// If expr is 0, size optimise the opcode. Generally the lower
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// 6 bits of the opcode for expr(ax) are 101rrr where rrr=the
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// number of the register, then followed by a word containing
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// 'expr'. We need to change that to 010rrr.
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if ((siz & 0x8000) == 0)
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{
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chptr_opcode[0] &= ((0xFFC7 >> 8) & 255); // mask off bits
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chptr_opcode[1] &= 0xFFC7 & 255; // mask off bits
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chptr_opcode[0] |= ((0x0010 >> 8) & 255); // slap in 010 bits
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chptr_opcode[1] |= 0x0010 & 255; // slap in 010 bits
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}
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else
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{
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// Special case for move ea,ea: there are two ea fields
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// there and we get a signal if it's the second ea field
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// from m_ea - siz's 16th bit is set
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chptr_opcode[0] &= ((0xFE3F >> 8) & 255); // mask off bits
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chptr_opcode[1] &= 0xFE3F & 255; // mask off bits
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chptr_opcode[0] |= ((0x0080 >> 8) & 255); // slap in 010 bits
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chptr_opcode[1] |= 0x0080 & 255; // slap in 010 bits
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}
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if (optim_warn_flag)
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warn("o3: 0(An) converted to (An)");
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return OK;
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}
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if ((v + 0x8000) >= 0x18000)
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return error(range_error);
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D_word(v);
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}
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else
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{
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// Arrange for fixup later on
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AddFixup(FU_WORD | FU_SEXT, sloc, aNexpr);
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D_word(0);
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}
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break;
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case PCDISP:
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if (w)
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{
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// Just deposit it
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if ((aNexattr & TDB) == cursect)
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v -= (uint32_t)sloc;
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else if ((aNexattr & TDB) != ABS)
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error(rel_error);
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if (v + 0x8000 >= 0x10000)
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return error(range_error);
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D_word(v);
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}
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else
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{
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// Arrange for fixup later on
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AddFixup(FU_WORD | FU_SEXT | FU_PCREL, sloc, aNexpr);
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D_word(0);
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}
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break;
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case AINDEXED:
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// Compute ixreg and size+scale
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w = (WORD)((aNixreg << 12) | aNixsiz);
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if (aNexattr & DEFINED)
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{
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// Deposit a byte...
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if (tdb)
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// Can't mark bytes
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return error(abs_error);
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if (v + 0x80 >= 0x180)
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return error(range_error);
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w |= v & 0xFF;
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D_word(w);
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}
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else
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{
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// Fixup the byte later
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AddFixup(FU_BYTE | FU_SEXT, sloc + 1, aNexpr);
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D_word(w);
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}
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break;
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case PCINDEXED:
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// Compute ixreg and size+scale
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w = (WORD)((aNixreg << 12) | aNixsiz);
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if (aNexattr & DEFINED)
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{
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// Deposit a byte...
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if ((aNexattr & TDB) == cursect)
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v -= (uint32_t)sloc;
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else if ((aNexattr & TDB) != ABS)
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error(rel_error);
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if (v + 0x80 >= 0x100)
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return error(range_error);
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w |= v & 0xFF;
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D_word(w);
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}
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else
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{
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// Fixup the byte later
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AddFixup(FU_WBYTE | FU_SEXT | FU_PCREL, sloc, aNexpr);
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D_word(w);
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}
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break;
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case IMMED:
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switch (siz)
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{
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case SIZB:
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if (w)
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{
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if (tdb)
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return error("illegal byte-sized relative reference");
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if (v + 0x100 >= 0x200)
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return error(range_error);
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D_word(v & 0xFF);
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}
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else
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{
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AddFixup(FU_BYTE | FU_SEXT, sloc + 1, aNexpr);
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D_word(0);
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}
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break;
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case SIZW:
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case SIZN:
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if (w)
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{
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if (v + 0x10000 >= 0x20000)
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return error(range_error);
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if (tdb)
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MarkRelocatable(cursect, sloc, tdb, MWORD, NULL);
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D_word(v);
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}
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else
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{
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AddFixup(FU_WORD | FU_SEXT, sloc, aNexpr);
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D_word(0);
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}
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break;
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case SIZL:
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if (w)
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{
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if (tdb)
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MarkRelocatable(cursect, sloc, tdb, MLONG, NULL);
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D_long(v);
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}
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else
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{
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AddFixup(FU_LONG, sloc, aNexpr);
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D_long(0);
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}
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break;
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case SIZS:
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// 68881/68882/68040 only
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if (w)
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{
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//Would a floating point value *ever* need to be fixed up as if it were an address? :-P
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// if (tdb)
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// MarkRelocatable(cursect, sloc, tdb, MSINGLE, NULL);
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// The value passed back from expr() is an internal C double;
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// so we have to access it as such then convert it to an
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// IEEE-754 float so we can store it as such in the instruction
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// stream here.
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PTR p;
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p.u64 = &aNexval;
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float f = (float)*p.dp;
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uint32_t ieee754 = FloatToIEEE754(f);
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D_long(ieee754);
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}
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else
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{
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AddFixup(FU_FLOATSING, sloc, aNexpr);
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D_long(0); // IEEE-754 zero is all zeroes
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}
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break;
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case SIZD:
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// 68881/68882/68040 only
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if (w)
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{
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//Would a floating point value *ever* need to be fixed up as if it were an address? :-P
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// if (tdb)
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// MarkRelocatable(cursect, sloc, tdb, MDOUBLE, NULL);
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PTR p;
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p.u64 = &aNexval;
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double d = *p.dp;
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uint64_t ieee754 = DoubleToIEEE754(d);
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D_quad(ieee754);
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}
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else
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{
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AddFixup(FU_FLOATDOUB, sloc, aNexpr);
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D_quad(0LL); // IEEE-754 zero is all zeroes
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}
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break;
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case SIZX:
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// 68881/68882/68040 only
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if (w)
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{
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//Would a floating point value *ever* need to be fixed up as if it were an address? :-P
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// if (tdb)
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// MarkRelocatable(cursect, sloc, tdb, MEXTEND, NULL);
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PTR p;
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p.u64 = &aNexval;
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DoubleToExtended(*p.dp, extDbl);
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D_extend(extDbl);
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}
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else
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{
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// Why would this be anything other than a floating point
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// expression??? Even if there were an undefined symbol in
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// the expression, how would that be relevant? I can't see
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// any use case where this would make sense.
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AddFixup(FU_FLOATDOUB, sloc, aNexpr);
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memset(extDbl, 0, 12);
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D_extend(extDbl);
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}
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break;
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default:
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// IMMED size problem
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interror(1);
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}
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break;
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case SIZP:
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// 68881/68882/68040 only
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return error("Sorry, .p constant format is not implemented yet!");
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break;
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case ABSW:
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if (w) // Defined
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{
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if (tdb)
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MarkRelocatable(cursect, sloc, tdb, MWORD, NULL);
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if (v + 0x8000 >= 0x10000)
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return error(range_error);
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D_word(v);
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}
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else
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{
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AddFixup(FU_WORD | FU_SEXT, sloc, aNexpr);
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D_word(0);
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}
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break;
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case ABSL:
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if (w) // Defined
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{
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if (CHECK_OPTS(OPT_PC_RELATIVE))
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{
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if ((aNexattr & (DEFINED | REFERENCED | EQUATED)) == (DEFINED | REFERENCED))
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return error("relocation not allowed when o10 is enabled");
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}
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if (tdb)
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MarkRelocatable(cursect, sloc, tdb, MLONG, NULL);
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D_long(v);
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}
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else
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{
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AddFixup(FU_LONG, sloc, aNexpr);
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D_long(0);
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}
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break;
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case DINDW:
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D_word((0x190 | (aNixreg << 12)));
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break;
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case DINDL:
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D_word((0x990 | (aNixreg << 12)));
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break;
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case ABASE:
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case MEMPOST:
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case MEMPRE:
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case PCBASE:
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case PCMPOST:
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case PCMPRE:
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D_word(aNexten);
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// Deposit bd (if not suppressed)
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if ((aNexten & 0x0030) == EXT_BDSIZE0)
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{
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// Don't deposit anything (suppressed)
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}
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else if ((aNexten & 0x0030) == EXT_BDSIZEW)
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{
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// Deposit word bd
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if (wbd)
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{
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// Just deposit it
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if (tdb)
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MarkRelocatable(cursect, sloc, tdbbd, MWORD, NULL);
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if (vbd + 0x8000 >= 0x10000)
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return error(range_error);
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D_word(vbd);
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}
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else
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{
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// Arrange for fixup later on
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AddFixup(FU_WORD | FU_SEXT | FU_PCRELX, sloc, aNbexpr);
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D_word(0);
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}
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}
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else
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{
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// Deposit long bd
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if (wbd)
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{
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// Just deposit it
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if (tdbbd)
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MarkRelocatable(cursect, sloc, tdbbd, MLONG, NULL);
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D_long(vbd);
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}
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else
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{
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// Arrange for fixup later on
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AddFixup(FU_LONG, sloc, aNbexpr);
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D_long(0);
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}
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}
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// Deposit od (if not suppressed)
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if ((aNexten & 7) == EXT_IISPRE0 || (aNexten & 7) == EXT_IISPREN
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|| (aNexten & 7) == EXT_IISNOIN || (aNexten & 7) == EXT_IISPOSN)
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{
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// Don't deposit anything (suppressed)
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}
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else if ((aNexten & 7) == EXT_IISPREW
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|| (aNexten & 7) == EXT_IISPOSW || (aNexten & 7) == EXT_IISNOIW)
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{
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// Deposit word od
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if (w)
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{
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// Just deposit it
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if (tdb)
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MarkRelocatable(cursect, sloc, tdb, MWORD, NULL);
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if (v + 0x8000 >= 0x10000)
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return error(range_error);
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D_word(v);
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}
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else
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{
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// Arrange for fixup later on
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AddFixup(FU_WORD | FU_SEXT, sloc, aNexpr);
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D_word(0);
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}
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}
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else
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{
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// Deposit long od
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if (w)
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{
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// Just deposit it
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if (tdb)
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MarkRelocatable(cursect, sloc, tdb, MLONG, NULL);
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D_long(v);
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}
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else
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{
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// Arrange for fixup later on
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AddFixup(FU_LONG | FU_SEXT, sloc, aNexpr);
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D_long(0);
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}
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}
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break;
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//return error("unsupported 68020 addressing mode");
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default:
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// Bad addressing mode in ea gen
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interror(3);
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}
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return OK;
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}
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// Undefine dirty macros
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#undef eaNgen
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#undef amN
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#undef aNexattr
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#undef aNexval
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#undef aNexpr
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#undef aNixreg
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#undef aNixsiz
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#undef aNexten
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#undef aNbexpr
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#undef aNbdexval
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#undef aNbdexattr
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#undef AnESYM
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