mirror of http://shamusworld.gotdns.org/git/rmac
Cleanup of codebase and initial commit of 56K assembler by ggn.
There's still a ways to go before this will work properly as we need to
add proper fixup handling and origin (".org") bookkeeping. As it is now,
the addition of all the miscellaneous bits and bobs to support the main
56K assembler are in place but they don't cause any regressions to the
existing assemblers already present in RMAC. Stay tuned for Round 2!
This commit is contained in:
Shamus Hammons
parent
790cd95291
commit
30a2086548
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@ -1,7 +1,7 @@
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68kgen
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68kgen.o
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68ktab.h
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68kmn
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68k.tab
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6502kw.h
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opkw.h
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*.o
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159
6502.c
159
6502.c
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@ -21,6 +21,9 @@
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#include "sect.h"
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#include "token.h"
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#define DEF_KW
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#include "kwtab.h"
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#define UPSEG_SIZE 0x10010L // size of 6502 code buffer, 64K+16bytes
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// Internal vars
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@ -50,83 +53,83 @@ char strtoa8[128]; // ASCII to Atari 800 internal conversion table
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#define A65_IMMEDH 12
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#define A65_IMMEDL 13
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#define NMACHOPS 56 // Number of machine ops
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#define NMODES 14 // Number of addressing modes
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#define NOP 0xEA // 6502 NOP instruction
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#define ILLEGAL 0xFF // 'Illegal instr' marker
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#define END65 0xFF // End-of-an-instr-list
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#define NMACHOPS 56 // Number of machine ops
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#define NMODES 14 // Number of addressing modes
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#define NOP 0xEA // 6502 NOP instruction
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#define ILLEGAL 0xFF // 'Illegal instr' marker
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#define END65 0xFF // End-of-an-instr-list
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static char imodes[] =
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{
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A65_IMMED, 0x69, A65_ABS, 0x6d, A65_ZP, 0x65, A65_INDX, 0x61, A65_INDY, 0x71,
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A65_ZPX, 0x75, A65_ABSX, 0x7d, A65_ABSY, 0x79, END65,
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A65_IMMED, 0x29, A65_ABS, 0x2d, A65_ZP, 0x25, A65_INDX, 0x21, A65_INDY, 0x31,
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A65_ZPX, 0x35, A65_ABSX, 0x3d, A65_ABSY, 0x39, END65,
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A65_ABS, 0x0e, A65_ZP, 0x06, A65_IMPL, 0x0a, A65_ZPX, 0x16, A65_ABSX,
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0x1e, END65,
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A65_IMMED, 0x69, A65_ABS, 0x6D, A65_ZP, 0x65, A65_INDX, 0x61, A65_INDY, 0x71,
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A65_ZPX, 0x75, A65_ABSX, 0x7D, A65_ABSY, 0x79, END65,
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A65_IMMED, 0x29, A65_ABS, 0x2D, A65_ZP, 0x25, A65_INDX, 0x21, A65_INDY, 0x31,
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A65_ZPX, 0x35, A65_ABSX, 0x3D, A65_ABSY, 0x39, END65,
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A65_ABS, 0x0E, A65_ZP, 0x06, A65_IMPL, 0x0A, A65_ZPX, 0x16, A65_ABSX,
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0x1E, END65,
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A65_REL, 0x90, END65,
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A65_REL, 0xb0, END65,
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A65_REL, 0xf0, END65,
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A65_REL, 0xd0, END65,
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A65_REL, 0xB0, END65,
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A65_REL, 0xF0, END65,
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A65_REL, 0xD0, END65,
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A65_REL, 0x30, END65,
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A65_REL, 0x10, END65,
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A65_REL, 0x50, END65,
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A65_REL, 0x70, END65,
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A65_ABS, 0x2c, A65_ZP, 0x24, END65,
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A65_ABS, 0x2C, A65_ZP, 0x24, END65,
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A65_IMPL, 0x00, END65,
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A65_IMPL, 0x18, END65,
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A65_IMPL, 0xd8, END65,
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A65_IMPL, 0xD8, END65,
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A65_IMPL, 0x58, END65,
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A65_IMPL, 0xb8, END65,
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A65_IMMED, 0xc9, A65_ABS, 0xcd, A65_ZP, 0xc5, A65_INDX, 0xc1, A65_INDY, 0xd1,
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A65_ZPX, 0xd5, A65_ABSX, 0xdd, A65_ABSY, 0xd9, END65,
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A65_IMMED, 0xe0, A65_ABS, 0xec, A65_ZP, 0xe4, END65,
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A65_IMMED, 0xc0, A65_ABS, 0xcc, A65_ZP, 0xc4, END65,
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A65_ABS, 0xce, A65_ZP, 0xc6, A65_ZPX, 0xd6, A65_ABSX, 0xde, END65,
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A65_IMPL, 0xca, END65,
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A65_IMPL, 0xB8, END65,
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A65_IMMED, 0xC9, A65_ABS, 0xCD, A65_ZP, 0xC5, A65_INDX, 0xC1, A65_INDY, 0xD1,
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A65_ZPX, 0xD5, A65_ABSX, 0xDD, A65_ABSY, 0xD9, END65,
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A65_IMMED, 0xE0, A65_ABS, 0xEC, A65_ZP, 0xE4, END65,
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A65_IMMED, 0xC0, A65_ABS, 0xCC, A65_ZP, 0xC4, END65,
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A65_ABS, 0xCE, A65_ZP, 0xC6, A65_ZPX, 0xD6, A65_ABSX, 0xDE, END65,
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A65_IMPL, 0xCA, END65,
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A65_IMPL, 0x88, END65,
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A65_IMMED, 0x49, A65_ABS, 0x4d, A65_ZP, 0x45, A65_INDX, 0x41, A65_INDY, 0x51,
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A65_ZPX, 0x55, A65_ABSX, 0x5d, A65_ABSY, 0x59, END65,
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A65_ABS, 0xee, A65_ZP, 0xe6, A65_ZPX, 0xf6, A65_ABSX, 0xfe, END65,
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A65_IMPL, 0xe8, END65,
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A65_IMPL, 0xc8, END65,
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A65_ABS, 0x4c, A65_IND, 0x6c, END65,
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A65_IMMED, 0x49, A65_ABS, 0x4D, A65_ZP, 0x45, A65_INDX, 0x41, A65_INDY, 0x51,
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A65_ZPX, 0x55, A65_ABSX, 0x5D, A65_ABSY, 0x59, END65,
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A65_ABS, 0xEE, A65_ZP, 0xE6, A65_ZPX, 0xF6, A65_ABSX, 0xFE, END65,
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A65_IMPL, 0xE8, END65,
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A65_IMPL, 0xC8, END65,
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A65_ABS, 0x4C, A65_IND, 0x6C, END65,
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A65_ABS, 0x20, END65,
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A65_IMMED, 0xa9, A65_ABS, 0xad, A65_ZP, 0xa5, A65_INDX, 0xa1, A65_INDY, 0xb1,
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A65_ZPX, 0xb5, A65_ABSX, 0xbd, A65_ABSY, 0xb9, A65_IMMEDH, 0xa9, A65_IMMEDL, 0xa9, END65,
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A65_IMMED, 0xa2, A65_ABS, 0xae, A65_ZP, 0xa6, A65_ABSY, 0xbe,
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A65_ZPY, 0xb6, A65_IMMEDH, 0xa2, A65_IMMEDL, 0xa2, END65,
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A65_IMMED, 0xa0, A65_ABS, 0xac, A65_ZP, 0xa4, A65_ZPX, 0xb4,
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A65_ABSX, 0xbc, A65_IMMEDH, 0xa0, A65_IMMEDL, 0xa0, END65,
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A65_ABS, 0x4e, A65_ZP, 0x46, A65_IMPL, 0x4a, A65_ZPX, 0x56,
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A65_ABSX, 0x5e, END65,
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A65_IMPL, 0xea, END65,
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A65_IMMED, 0x09, A65_ABS, 0x0d, A65_ZP, 0x05, A65_INDX, 0x01, A65_INDY, 0x11,
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A65_ZPX, 0x15, A65_ABSX, 0x1d, A65_ABSY, 0x19, END65,
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A65_IMMED, 0xA9, A65_ABS, 0xAD, A65_ZP, 0xA5, A65_INDX, 0xA1, A65_INDY, 0xB1,
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A65_ZPX, 0xB5, A65_ABSX, 0xBD, A65_ABSY, 0xB9, A65_IMMEDH, 0xA9, A65_IMMEDL, 0xA9, END65,
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A65_IMMED, 0xA2, A65_ABS, 0xAE, A65_ZP, 0xA6, A65_ABSY, 0xBE,
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A65_ZPY, 0xB6, A65_IMMEDH, 0xA2, A65_IMMEDL, 0xA2, END65,
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A65_IMMED, 0xA0, A65_ABS, 0xAC, A65_ZP, 0xA4, A65_ZPX, 0xB4,
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A65_ABSX, 0xBC, A65_IMMEDH, 0xA0, A65_IMMEDL, 0xA0, END65,
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A65_ABS, 0x4E, A65_ZP, 0x46, A65_IMPL, 0x4A, A65_ZPX, 0x56,
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A65_ABSX, 0x5E, END65,
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A65_IMPL, 0xEA, END65,
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A65_IMMED, 0x09, A65_ABS, 0x0D, A65_ZP, 0x05, A65_INDX, 0x01, A65_INDY, 0x11,
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A65_ZPX, 0x15, A65_ABSX, 0x1D, A65_ABSY, 0x19, END65,
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A65_IMPL, 0x48, END65,
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A65_IMPL, 0x08, END65,
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A65_IMPL, 0x68, END65,
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A65_IMPL, 0x28, END65,
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A65_ABS, 0x2e, A65_ZP, 0x26, A65_IMPL, 0x2a, A65_ZPX, 0x36,
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A65_ABSX, 0x3e, END65,
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A65_ABS, 0x6e, A65_ZP, 0x66, A65_IMPL, 0x6a, A65_ZPX, 0x76,
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A65_ABSX, 0x7e, END65,
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A65_ABS, 0x2E, A65_ZP, 0x26, A65_IMPL, 0x2A, A65_ZPX, 0x36,
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A65_ABSX, 0x3E, END65,
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A65_ABS, 0x6E, A65_ZP, 0x66, A65_IMPL, 0x6A, A65_ZPX, 0x76,
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A65_ABSX, 0x7E, END65,
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A65_IMPL, 0x40, END65,
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A65_IMPL, 0x60, END65,
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A65_IMMED, 0xe9, A65_ABS, 0xed, A65_ZP, 0xe5, A65_INDX, 0xe1, A65_INDY, 0xf1,
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A65_ZPX, 0xf5, A65_ABSX, 0xfd, A65_ABSY, 0xf9, END65,
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A65_IMMED, 0xE9, A65_ABS, 0xED, A65_ZP, 0xE5, A65_INDX, 0xE1, A65_INDY, 0xF1,
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A65_ZPX, 0xF5, A65_ABSX, 0xFD, A65_ABSY, 0xF9, END65,
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A65_IMPL, 0x38, END65,
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A65_IMPL, 0xf8, END65,
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A65_IMPL, 0xF8, END65,
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A65_IMPL, 0x78, END65,
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A65_ABS, 0x8d, A65_ZP, 0x85, A65_INDX, 0x81, A65_INDY, 0x91, A65_ZPX, 0x95,
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A65_ABSX, 0x9d, A65_ABSY, 0x99, END65,
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A65_ABS, 0x8e, A65_ZP, 0x86, A65_ZPY, 0x96, END65,
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A65_ABS, 0x8c, A65_ZP, 0x84, A65_ZPX, 0x94, END65,
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A65_IMPL, 0xaa, END65,
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A65_IMPL, 0xa8, END65,
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A65_IMPL, 0xba, END65,
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A65_IMPL, 0x8a, END65,
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A65_IMPL, 0x9a, END65,
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A65_ABS, 0x8D, A65_ZP, 0x85, A65_INDX, 0x81, A65_INDY, 0x91, A65_ZPX, 0x95,
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A65_ABSX, 0x9D, A65_ABSY, 0x99, END65,
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A65_ABS, 0x8E, A65_ZP, 0x86, A65_ZPY, 0x96, END65,
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A65_ABS, 0x8C, A65_ZP, 0x84, A65_ZPX, 0x94, END65,
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A65_IMPL, 0xAA, END65,
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A65_IMPL, 0xA8, END65,
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A65_IMPL, 0xBA, END65,
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A65_IMPL, 0x8A, END65,
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A65_IMPL, 0x9A, END65,
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A65_IMPL, 0x98, END65
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};
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@ -264,6 +267,14 @@ void m6502cg(int op)
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amode = A65_IMPL;
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break;
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case KW_A:
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if (tok[1] != EOL)
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goto badmode;
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amode = A65_IMPL;
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tok++;
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break;
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case '#':
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tok++;
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@ -307,6 +318,7 @@ void m6502cg(int op)
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{
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// (foo),y
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tok++;
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#if 0
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p = string[tok[1]];
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// Sleazo tolower() -----------------vvvvvvvvvvv
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@ -315,6 +327,15 @@ void m6502cg(int op)
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tok += 2;
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amode = A65_INDY;
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#else
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if (tok[0] == KW_Y)
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amode = A65_INDY;
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if (tok[1] != EOL)
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goto badmode;
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tok++;
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#endif
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}
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else
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amode = A65_IND;
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@ -421,6 +442,7 @@ not_coinop:
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else if (*tok == ',')
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{
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tok++;
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#if 0
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p = string[tok[1]];
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if (*tok != SYMBOL || p[1] != EOS)
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@ -441,6 +463,21 @@ not_coinop:
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amode = A65_ABSY;
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else
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goto badmode;
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#else
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if (tok[0] == KW_X)
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{
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amode = A65_ABSX;
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tok++;
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}
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else if (tok[0] == KW_Y)
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{
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amode = A65_ABSY;
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tok++;
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}
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if (tok[0] != EOL)
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goto badmode;
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#endif
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}
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else
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goto badmode;
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@ -568,9 +605,9 @@ badmode:
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D_rword(eval);
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break;
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//
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// Deposit 3 NOPs for illegal things
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//
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//
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// Deposit 3 NOPs for illegal things (why 3? why not 30? or zero?)
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//
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default:
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case ILLEGAL:
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for(i=0; i<3; i++)
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@ -583,6 +620,7 @@ badmode:
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if (sloc > 0x10000L)
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fatal("6502 code pointer > 64K");
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//Now why use this instead of at_eol()?
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if (*tok != EOL)
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error(extra_stuff);
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}
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@ -609,6 +647,9 @@ void m6502obj(int ofd)
|
|||
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for(uint16_t * l=&orgmap[0][0]; l<currentorg; l+=2)
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{
|
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/*
|
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Why are we assuming endianness here? This is retarded
|
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*/
|
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exeheader[1] = l[0];
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exeheader[2] = l[1] - 1;
|
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|
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|
|
|
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11
68kgen.c
11
68kgen.c
|
|
@ -76,12 +76,11 @@ int main(int argc, char ** argv)
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void procln(int namc, char ** namv)
|
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{
|
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int i, j;
|
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char * s;
|
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|
||||
// alias for previous entry
|
||||
if (namc == 1)
|
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{
|
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fprintf(kfp, "%s\t%d\n", namv[0], kwnum-1+1000);
|
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fprintf(kfp, "%s\t%d\n", namv[0], kwnum - 1 + 1000);
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return;
|
||||
}
|
||||
|
||||
|
|
@ -99,7 +98,7 @@ void procln(int namc, char ** namv)
|
|||
|
||||
if (*namv[1] == '!')
|
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printf("CGSPECIAL");
|
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else for (s = namv[1], i=0; *s; ++s)
|
||||
else for(char * s=namv[1], i=0; *s; s++)
|
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printf("%sSIZ%c", (i++ ? "|" : ""), *s);
|
||||
|
||||
printf(", %s, %s, ", namv[2], namv[3]);
|
||||
|
|
@ -107,12 +106,12 @@ void procln(int namc, char ** namv)
|
|||
// enforce little fascist percent signs
|
||||
if (*namv[4] == '%')
|
||||
{
|
||||
for(i=1, j=0; i<17; ++i)
|
||||
for(i=1, j=0; i<17; i++)
|
||||
{
|
||||
j <<= 1;
|
||||
|
||||
if (namv[4][i] == '1' || isupper(namv[4][i]))
|
||||
++j;
|
||||
j++;
|
||||
}
|
||||
|
||||
printf("0x%04x, ", j);
|
||||
|
|
@ -121,7 +120,7 @@ void procln(int namc, char ** namv)
|
|||
printf("%s, ", namv[4]);
|
||||
|
||||
if (namc == 7 && *namv[6] == '+')
|
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printf("%d, ", kwnum+1);
|
||||
printf("%d, ", kwnum + 1);
|
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else
|
||||
printf("0, ");
|
||||
|
||||
|
|
|
|||
80
direct.c
80
direct.c
|
|
@ -218,10 +218,11 @@ int d_org(void)
|
|||
{
|
||||
uint64_t address;
|
||||
|
||||
if (!rgpu && !rdsp && !robjproc && !m6502)
|
||||
return error(".org permitted only in GPU/DSP/OP and 6502 sections");
|
||||
if (!rgpu && !rdsp && !robjproc && !m6502 && !dsp56001)
|
||||
return error(".org permitted only in GPU/DSP/OP, 56001 and 6502 sections");
|
||||
|
||||
if (abs_expr(&address) == ERROR)
|
||||
// M56K can leave the expression off the org for some reason :-/
|
||||
if ((abs_expr(&address) == ERROR) && !dsp56001)
|
||||
{
|
||||
error("cannot determine org'd address");
|
||||
return ERROR;
|
||||
|
|
@ -232,9 +233,9 @@ int d_org(void)
|
|||
orgaddr = address;
|
||||
orgactive = 1;
|
||||
}
|
||||
else
|
||||
else if (m6502)
|
||||
{
|
||||
// 6502. We also kludge `lsloc' so the listing generator doesn't try
|
||||
// 6502. We also kludge 'lsloc' so the listing generator doesn't try
|
||||
// to spew out megabytes.
|
||||
if (address > 0xFFFF)
|
||||
return error(range_error);
|
||||
|
|
@ -251,9 +252,12 @@ int d_org(void)
|
|||
chptr = scode->chptr + address;
|
||||
orgaddr = address;
|
||||
orgactive = 1;
|
||||
at_eol();
|
||||
}
|
||||
else if (dsp56001)
|
||||
{
|
||||
}
|
||||
|
||||
at_eol();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -290,25 +294,39 @@ int d_print(void)
|
|||
case '/':
|
||||
formatting = 1;
|
||||
|
||||
if (tok[1] != SYMBOL)
|
||||
// "X" & "L" get tokenized now... :-/ Probably should look into preventing this kind of thing from happening (was added with DSP56K code)
|
||||
if ((tok[1] != SYMBOL) && (tok[1] != KW_L) && (tok[1] != KW_X))
|
||||
goto token_err;
|
||||
|
||||
// strcpy(prntstr, (char *)tok[2]);
|
||||
strcpy(prntstr, string[tok[2]]);
|
||||
|
||||
switch(prntstr[0])
|
||||
if (tok[1] == KW_L)
|
||||
{
|
||||
case 'l': case 'L': wordlong = 1; break;
|
||||
case 'w': case 'W': wordlong = 0; break;
|
||||
case 'x': case 'X': outtype = 0; break;
|
||||
case 'd': case 'D': outtype = 1; break;
|
||||
case 'u': case 'U': outtype = 2; break;
|
||||
default:
|
||||
error("unknown print format flag");
|
||||
return ERROR;
|
||||
wordlong = 1;
|
||||
tok += 2;
|
||||
}
|
||||
else if (tok[1] == KW_X)
|
||||
{
|
||||
outtype = 0;
|
||||
tok += 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
strcpy(prntstr, string[tok[2]]);
|
||||
|
||||
switch(prntstr[0])
|
||||
{
|
||||
case 'l': case 'L': wordlong = 1; break;
|
||||
case 'w': case 'W': wordlong = 0; break;
|
||||
case 'x': case 'X': outtype = 0; break;
|
||||
case 'd': case 'D': outtype = 1; break;
|
||||
case 'u': case 'U': outtype = 2; break;
|
||||
default:
|
||||
error("unknown print format flag");
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
tok += 3;
|
||||
}
|
||||
|
||||
tok += 3;
|
||||
break;
|
||||
case ',':
|
||||
tok++;
|
||||
|
|
@ -349,7 +367,7 @@ int d_print(void)
|
|||
return 0;
|
||||
|
||||
token_err:
|
||||
error("illegal print token");
|
||||
error("illegal print token [@ '%s']", prntstr);
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
|
|
@ -958,7 +976,7 @@ int d_ds(WORD siz)
|
|||
|
||||
uint64_t eval;
|
||||
|
||||
if (cursect != M6502)
|
||||
if ((cursect & (M6502 | M56KPXYL)) == 0)
|
||||
{
|
||||
if ((siz != SIZB) && (sloc & 1)) // Automatic .even
|
||||
auto_even();
|
||||
|
|
@ -1036,7 +1054,7 @@ int d_dc(WORD siz)
|
|||
for(p=string[tok[1]]; *p!=EOS; p++)
|
||||
D_byte(*p);
|
||||
}
|
||||
else if(*tok == STRINGA8)
|
||||
else if (*tok == STRINGA8)
|
||||
{
|
||||
for(p=string[tok[1]]; *p!=EOS; p++)
|
||||
D_byte(strtoa8[*p]);
|
||||
|
|
@ -1496,7 +1514,7 @@ int d_nlist(void)
|
|||
//
|
||||
int d_68000(void)
|
||||
{
|
||||
rgpu = rdsp = robjproc = 0;
|
||||
rgpu = rdsp = robjproc = dsp56001 = 0;
|
||||
// Switching from gpu/dsp sections should reset any ORG'd Address
|
||||
orgactive = 0;
|
||||
orgwarning = 0;
|
||||
|
|
@ -1586,11 +1604,18 @@ int d_nofpu(void)
|
|||
|
||||
|
||||
//
|
||||
// DSP56001
|
||||
// .56001 - Switch to DSP56001 assembler
|
||||
//
|
||||
int d_56001(void)
|
||||
{
|
||||
return error("Not yet, child. Be patient.");
|
||||
dsp56001 = 1;
|
||||
rgpu = rdsp = robjproc = 0;
|
||||
SaveSection();
|
||||
|
||||
if (obj_format == LOD || obj_format == P56)
|
||||
SwitchSection(M56001P);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1615,6 +1640,7 @@ int d_gpu(void)
|
|||
rgpu = 1; // Set GPU assembly
|
||||
rdsp = 0; // Unset DSP assembly
|
||||
robjproc = 0; // Unset OP assembly
|
||||
dsp56001 = 0; // Unset 56001 assembly
|
||||
regbank = BANK_N; // Set no default register bank
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1641,6 +1667,7 @@ int d_dsp(void)
|
|||
rdsp = 1; // Set DSP assembly
|
||||
rgpu = 0; // Unset GPU assembly
|
||||
robjproc = 0; // Unset OP assembly
|
||||
dsp56001 = 0; // Unset 56001 assembly
|
||||
regbank = BANK_N; // Set no default register bank
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1913,6 +1940,7 @@ int d_objproc(void)
|
|||
robjproc = 1; // Set OP assembly
|
||||
rgpu = 0; // Unset GPU assembly
|
||||
rdsp = 0; // Unset DSP assembly
|
||||
dsp56001 = 0; // Unset 56001 assembly
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
//
|
||||
// RMAC - Reboot's Macro Assembler for all Atari computers
|
||||
// DSP56K.C - General DSP56001 routines
|
||||
// Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
|
||||
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
|
||||
// Source utilised with the kind permission of Landon Dyer
|
||||
//
|
||||
|
||||
#include "rmac.h"
|
||||
#include "dsp56k.h"
|
||||
|
||||
DSP_ORG dsp_orgmap[1024]; // Mark all 56001 org changes
|
||||
DSP_ORG * dsp_currentorg = &dsp_orgmap[0];
|
||||
int dsp_written_data_in_current_org = 0;
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
//
|
||||
// RMAC - Reboot's Macro Assembler for all Atari computers
|
||||
// DSP56K.H - General DSP56001 routines
|
||||
// Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
|
||||
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
|
||||
// Source utilised with the kind permission of Landon Dyer
|
||||
//
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "rmac.h"
|
||||
#include "sect.h"
|
||||
|
||||
// Exported variables.
|
||||
#define DSP_MAX_RAM (32*3*1024) // 32k 24-bit words
|
||||
#define DSP_ORG struct dsp56001_orgentry
|
||||
|
||||
enum MEMTYPES
|
||||
{
|
||||
ORG_P,
|
||||
ORG_X,
|
||||
ORG_Y,
|
||||
ORG_L
|
||||
} ;
|
||||
|
||||
DSP_ORG
|
||||
{
|
||||
enum MEMTYPES memtype;
|
||||
uint8_t * start;
|
||||
uint8_t * end;
|
||||
uint32_t orgadr;
|
||||
CHUNK * chunk;
|
||||
};
|
||||
|
||||
extern DSP_ORG dsp_orgmap[1024]; // Mark all 56001 org changes
|
||||
extern DSP_ORG * dsp_currentorg;
|
||||
extern int dsp_written_data_in_current_org;
|
||||
|
||||
#define dprintf(...) p_buf += sprintf(p_buf, __VA_ARGS__)
|
||||
|
||||
// Exported functions
|
||||
|
||||
|
|
@ -0,0 +1,336 @@
|
|||
abs M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d110 dsp_ab d=(a=0, b=1)
|
||||
asl M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d010 dsp_ab d=(a=0, b=1)
|
||||
asr M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d010 dsp_ab d=(a=0, b=1)
|
||||
clr M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0001d011 dsp_ab d=(a=0, b=1)
|
||||
lsl M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d011 dsp_ab d=(a=0, b=1)
|
||||
lsr M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d011 dsp_ab d=(a=0, b=1)
|
||||
not M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0001d111 dsp_ab d=(a=0, b=1)
|
||||
addl M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d010 dsp_baab d=(b,a=0, a,b=1)
|
||||
addr M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d010 dsp_baab d=(b,a=0, a,b=1)
|
||||
add M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d000 dsp_baab + d=(a=0, b=1)
|
||||
- M_ALL48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd000 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
|
||||
cmp M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d101 dsp_baab + d=(a=0, b=1)
|
||||
- M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd101 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
|
||||
cmpm M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d111 dsp_baab + d=(a=0, b=1)
|
||||
- M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd111 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
|
||||
sub M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d100 dsp_baab + d=(a=0, b=1)
|
||||
- M_ALL48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd100 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
|
||||
tfr M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d001 dsp_baab + d=(a=0, b=1)
|
||||
- M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd001 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
|
||||
rnd M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0001d001 dsp_ab d=(a=0, b=1)
|
||||
rol M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d111 dsp_ab d=(a=0, b=1)
|
||||
ror M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d111 dsp_ab d=(a=0, b=1)
|
||||
subl M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d110 dsp_baab d=(b,a=0, a,b=1)
|
||||
subr M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d110 dsp_baab d=(b,a=0, a,b=1)
|
||||
tst M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0000d011 dsp_ab d=(a=0, b=1)
|
||||
enddo M_AM_NONE M_AM_NONE NOPARMO %000000000000000010001100 dsp_self
|
||||
illegal M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000101 dsp_self
|
||||
nop M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000000 dsp_self
|
||||
reset M_AM_NONE M_AM_NONE NOPARMO %000000000000000010000100 dsp_self
|
||||
rti M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000100 dsp_self
|
||||
rts M_AM_NONE M_AM_NONE NOPARMO %000000000000000000001100 dsp_self
|
||||
stop M_AM_NONE M_AM_NONE NOPARMO %000000000000000010000111 dsp_self
|
||||
swi M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000110 dsp_self
|
||||
wait M_AM_NONE M_AM_NONE NOPARMO %000000000000000010000110 dsp_self
|
||||
adc M_INP48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm001jd001 dsp_xyab j=(x=0, y=1), d=(a=0, b=1)
|
||||
sbc M_INP48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm001jd101 dsp_xyab s1 (j)=(x=0,y=1),s2 (d)=(a=0,b=1)
|
||||
and M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm01jjd110 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
|
||||
eor M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm01jjd011 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
|
||||
div M_ALU24 M_ACC56 NOPARMO %000000011000000001jjd000 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
|
||||
or M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm01jjd010 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
|
||||
andi M_DSPIM8 M_DSPPCU NOPARMO %00000000iiiiiiii101110ee dsp_immcr ee=(mr=0, ccr=1, omr=2)
|
||||
ori M_DSPIM8 M_DSPPCU NOPARMO %00000000iiiiiiii111110ee dsp_immcr ee=(mr=0, ccr=1, omr=2)
|
||||
tcc M_ACC56 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
ths M_ACC56 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tcs M_ACC56 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tlo M_ACC56 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tec M_ACC56 M_ACC56 NOPARMO %00000010010100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010010100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
teq M_ACC56 M_ACC56 NOPARMO %00000010101000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010101000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tes M_ACC56 M_ACC56 NOPARMO %00000010110100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010110100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tge M_ACC56 M_ACC56 NOPARMO %00000010000100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010000100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tgt M_ACC56 M_ACC56 NOPARMO %00000010011100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010011100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tlc M_ACC56 M_ACC56 NOPARMO %00000010011000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010011000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tle M_ACC56 M_ACC56 NOPARMO %00000010111100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010111100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tls M_ACC56 M_ACC56 NOPARMO %00000010111000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010111000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tlt M_ACC56 M_ACC56 NOPARMO %00000010100100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010100100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tmi M_ACC56 M_ACC56 NOPARMO %00000010101100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010101100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tne M_ACC56 M_ACC56 NOPARMO %00000010001000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010001000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tnr M_ACC56 M_ACC56 NOPARMO %00000010110000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010110000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tpl M_ACC56 M_ACC56 NOPARMO %00000010001100000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010001100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
tnn M_ACC56 M_ACC56 NOPARMO %00000010010000000jjjd000 dsp_baab + s1,d1 [s2,d2]
|
||||
- M_ALL48 M_ACC56 NOPARMO %00000010010000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
|
||||
jcc M_DSPABS12 M_AM_NONE NOPARMO %000011100000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100000 dsp_ea Jcc ea mmmrrr=ea
|
||||
jhs M_DSPABS12 M_AM_NONE NOPARMO %000011100000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100000 dsp_ea Jcc ea mmmrrr=ea
|
||||
jcs M_DSPABS12 M_AM_NONE NOPARMO %000011101000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101000 dsp_ea Jcc ea mmmrrr=ea
|
||||
jlo M_DSPABS12 M_AM_NONE NOPARMO %000011101000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101000 dsp_ea Jcc ea mmmrrr=ea
|
||||
jec M_DSPABS12 M_AM_NONE NOPARMO %000011100101aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100101 dsp_ea Jcc ea mmmrrr=ea
|
||||
jeq M_DSPABS12 M_AM_NONE NOPARMO %000011101010aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101010 dsp_ea Jcc ea mmmrrr=ea
|
||||
jes M_DSPABS12 M_AM_NONE NOPARMO %000011101101aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101101 dsp_ea Jcc ea mmmrrr=ea
|
||||
jge M_DSPABS12 M_AM_NONE NOPARMO %000011100001aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100001 dsp_ea Jcc ea mmmrrr=ea
|
||||
jgt M_DSPABS12 M_AM_NONE NOPARMO %000011100111aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100111 dsp_ea Jcc ea mmmrrr=ea
|
||||
jge M_DSPABS12 M_AM_NONE NOPARMO %000011100001aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100001 dsp_ea Jcc ea mmmrrr=ea
|
||||
jlc M_DSPABS12 M_AM_NONE NOPARMO %000011100110aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100110 dsp_ea Jcc ea mmmrrr=ea
|
||||
jle M_DSPABS12 M_AM_NONE NOPARMO %000011101111aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101111 dsp_ea Jcc ea mmmrrr=ea
|
||||
jls M_DSPABS12 M_AM_NONE NOPARMO %000011101110aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101110 dsp_ea Jcc ea mmmrrr=ea
|
||||
jlt M_DSPABS12 M_AM_NONE NOPARMO %000011101001aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101001 dsp_ea Jcc ea mmmrrr=ea
|
||||
jmi M_DSPABS12 M_AM_NONE NOPARMO %000011101011aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101011 dsp_ea Jcc ea mmmrrr=ea
|
||||
jne M_DSPABS12 M_AM_NONE NOPARMO %000011100010aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100010 dsp_ea Jcc ea mmmrrr=ea
|
||||
jnr M_DSPABS12 M_AM_NONE NOPARMO %000011101100aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101100 dsp_ea Jcc ea mmmrrr=ea
|
||||
jpl M_DSPABS12 M_AM_NONE NOPARMO %000011100011aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100011 dsp_ea Jcc ea mmmrrr=ea
|
||||
jnn M_DSPABS12 M_AM_NONE NOPARMO %000011100100aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100100 dsp_ea Jcc ea mmmrrr=ea
|
||||
jmp M_DSPABS12 M_AM_NONE NOPARMO %000011000000aaaaaaaaaaaa dsp_abs12 + JMP xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10000000 dsp_ea JMP ea (+optional 24bit address)
|
||||
jscc M_DSPABS12 M_AM_NONE NOPARMO %000011110000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jshs M_DSPABS12 M_AM_NONE NOPARMO %000011110000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jscs M_DSPABS12 M_AM_NONE NOPARMO %000011111000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jslo M_DSPABS12 M_AM_NONE NOPARMO %000011111000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsec M_DSPABS12 M_AM_NONE NOPARMO %000011110101aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100101 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jseq M_DSPABS12 M_AM_NONE NOPARMO %000011111010aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101010 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jses M_DSPABS12 M_AM_NONE NOPARMO %000011111101aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101101 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsge M_DSPABS12 M_AM_NONE NOPARMO %000011110001aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100001 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsgt M_DSPABS12 M_AM_NONE NOPARMO %000011110111aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100111 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jslc M_DSPABS12 M_AM_NONE NOPARMO %000011110110aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100110 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsle M_DSPABS12 M_AM_NONE NOPARMO %000011111111aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101111 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsls M_DSPABS12 M_AM_NONE NOPARMO %000011111110aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101110 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jslt M_DSPABS12 M_AM_NONE NOPARMO %000011111001aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101001 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsmi M_DSPABS12 M_AM_NONE NOPARMO %000011111011aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101011 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsne M_DSPABS12 M_AM_NONE NOPARMO %000011110010aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100010 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsnr M_DSPABS12 M_AM_NONE NOPARMO %000011111100aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101100 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jspl M_DSPABS12 M_AM_NONE NOPARMO %000011110011aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100011 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsnn M_DSPABS12 M_AM_NONE NOPARMO %000011110100aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100100 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
|
||||
jsr M_DSPABS12 M_AM_NONE NOPARMO %000011010000aaaaaaaaaaaa dsp_abs12 + JSR xxx aaaaaaaaaaaa=12bit address
|
||||
- C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10000000 dsp_ea JSR ea mmmrrr=ea (+optional 24bit address)
|
||||
neg M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d110 dsp_ab d=(a=0, b=1)
|
||||
bchg C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr0s0bbbbb dsp_ea_imm5 + bchg #n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa0s0bbbbb dsp_ea_imm5 + bchg #n,X:aa / bchg #n,Y:aa
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101110pppppp0s0bbbbb dsp_ea_imm5 + bchg #n,X:pp / bchg #n,Y:pp
|
||||
- C_DSPIM C_DD NOPARMO %00001011110001dd010bbbbb dsp_reg_imm5 + bchg #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DDD NOPARMO %0000101111001ddd010bbbbb dsp_reg_imm5 + bchg #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101111010ddd010bbbbb dsp_reg_imm5 + bchg #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101111011ddd010bbbbb dsp_reg_imm5 + bchg #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101111100ddd010bbbbb dsp_reg_imm5 + bchg #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101111111ddd010bbbbb dsp_reg_imm5 bchg #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
bclr C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr0s0bbbbb dsp_ea_imm5 + bclr #n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa0s0bbbbb dsp_ea_imm5 + bclr #n,X:aa / bclr #n,Y:aa
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101010pppppp0s0bbbbb dsp_ea_imm5 + bclr #n,X:pp / bclr #n,Y:pp
|
||||
- C_DSPIM C_DDD NOPARMO %0000101011001ddd010bbbbb dsp_reg_imm5 + bclr #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DD NOPARMO %00001010110001dd010bbbbb dsp_reg_imm5 + bclr #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101011010ddd010bbbbb dsp_reg_imm5 + bclr #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101011011ddd010bbbbb dsp_reg_imm5 + bclr #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101011100ddd010bbbbb dsp_reg_imm5 + bclr #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101011111ddd010bbbbb dsp_reg_imm5 bclr #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
bset C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr0s1bbbbb dsp_ea_imm5 + bset #n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa0s1bbbbb dsp_ea_imm5 + bset #n,X:aa / bset #n,Y:aa
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101010pppppp0s1bbbbb dsp_ea_imm5 + bset #n,X:pp / bset #n,Y:pp
|
||||
- C_DSPIM C_DD NOPARMO %00001010110001dd011bbbbb dsp_reg_imm5 + bset #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DDD NOPARMO %0000101011001ddd011bbbbb dsp_reg_imm5 + bset #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101011010ddd011bbbbb dsp_reg_imm5 + bset #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101011011ddd011bbbbb dsp_reg_imm5 + bset #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101011100ddd011bbbbb dsp_reg_imm5 + bset #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101011111ddd011bbbbb dsp_reg_imm5 bset #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
btst C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr0s1bbbbb dsp_ea_imm5 + btst#n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa0s1bbbbb dsp_ea_imm5 + btst #n,X:aa / btst #n,Y:aa
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101110pppppp0s1bbbbb dsp_ea_imm5 + btst #n,X:pp / btst #n,Y:pp
|
||||
- C_DSPIM C_DDD NOPARMO %0000101111001ddd011bbbbb dsp_reg_imm5 + btst #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DD NOPARMO %00001011110001dd011bbbbb dsp_reg_imm5 + btst #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101111010ddd011bbbbb dsp_reg_imm5 + btst #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101111011ddd011bbbbb dsp_reg_imm5 + btst #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101111100ddd011bbbbb dsp_reg_imm5 + btst #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101111111ddd011bbbbb dsp_reg_imm5 btst #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
do M_DSPEA C_DSPABS24 NOPARMO %0000011001mmmrrr0s000000 dsp_ea_abs16 + DO X:ea,expr / DO Y:ea,expr mmmrrr=ea, s=(X=0, Y=1), expr=16bit in extension word
|
||||
- M_DSPAA C_DSPABS24 NOPARMO %0000011000aaaaaa0s000000 dsp_ea_abs16 + DO X:aa,expr / DO Y:aa,expr aaaaaa=aa, s=(X=0, Y=1), expr=16bit in extension word
|
||||
- C_DSPIM C_DSPABS24 NOPARMO %00000110iiiiiiii1000hhhh dsp_imm12_abs16 + DO #xxx,expr hhhhiiiiiiii=12bit immediate, expr=16bit in extension word
|
||||
- M_ALU24 C_DSPABS24 NOPARMO %0000011011000ddd00000000 dsp_alu24_abs16 + DO S,expr x0, x1, y0, y1
|
||||
- C_DDD C_DSPABS24 NOPARMO %0000011011001ddd00000000 dsp_reg_abs16 + DO S,expr DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_TTT C_DSPABS24 NOPARMO %0000011011010ddd00000000 dsp_reg_abs16 + DO S,expr TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_NNN C_DSPABS24 NOPARMO %0000011011011ddd00000000 dsp_reg_abs16 + DO S,expr NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_FFF C_DSPABS24 NOPARMO %0000011011100ddd00000000 dsp_reg_abs16 + DO S,expr FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_GGG C_DSPABS24 NOPARMO %0000011011111ddd00000000 dsp_reg_abs16 DO S,expr GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
rep C_DSPIM M_AM_NONE NOPARMO %00000110iiiiiiii1010hhhh dsp_imm12 + rep #xx
|
||||
- M_DSPEA M_AM_NONE NOPARMO %0000011001mmmrrr0s100000 dsp_ea + rep x:ea / y:ea
|
||||
- M_DSPAA M_AM_NONE NOPARMO %0000011000aaaaaa0s100000 dsp_ea + rep x:aa / y:aa
|
||||
- M_ALU24 M_AM_NONE NOPARMO %0000011011000ddd00100000 dsp_alu24 + rep S,expr x0, x1, y0, y1
|
||||
- C_DDD M_AM_NONE NOPARMO %0000011011001ddd00100000 dsp_reg + rep S DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_TTT M_AM_NONE NOPARMO %0000011011010ddd00100000 dsp_reg + rep S TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_NNN M_AM_NONE NOPARMO %0000011011011ddd00100000 dsp_reg + rep S NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_FFF M_AM_NONE NOPARMO %0000011011100ddd00100000 dsp_reg + rep S FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_GGG M_AM_NONE NOPARMO %0000011011111ddd00100000 dsp_reg rep S GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
jsclr C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr1s0bbbbb dsp_ea_imm5_abs16 + JSCLR #n,X:ea,xxxx / #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa1s0bbbbb dsp_ea_imm5_abs16 + JSCLR #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101110pppppp1s0bbbbb dsp_ea_imm5_abs16 + JSCLR #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
|
||||
- C_DSPIM C_DD NOPARMO %00001011110001dd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DDD NOPARMO %0000101111001ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101111010ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101111011ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101111100ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101111101ddd000bbbbb dsp_reg_imm5_abs16 JSCLR #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
jset C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr1s1bbbbb dsp_ea_imm5_abs16 + JSET #n,X:ea,xxxx / #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa1s1bbbbb dsp_ea_imm5_abs16 + JSET #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101010pppppp1s1bbbbb dsp_ea_imm5_abs16 + JSET #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
|
||||
- C_DSPIM C_DD NOPARMO %00001010110001dd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DDD NOPARMO %0000101011001ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101011010ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101011011ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101011100ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101011101ddd001bbbbb dsp_reg_imm5_abs16 JSET #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
jsset C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr1s1bbbbb dsp_ea_imm5_abs16 + JSSET #n,X:ea,xxxx / JSSET #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa1s1bbbbb dsp_ea_imm5_abs16 + JSSET #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101110pppppp1s1bbbbb dsp_ea_imm5_abs16 + JSSET #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
|
||||
- C_DSPIM C_DD NOPARMO %00001011110001dd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DDD NOPARMO %0000101111001ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101111010ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101111011ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101111100ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101111101ddd001bbbbb dsp_reg_imm5_abs16 JSSET #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
jclr C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr1s0bbbbb dsp_ea_imm5_abs16 + JCLR #n,X:ea,xxxx / #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa1s0bbbbb dsp_ea_imm5_abs16 + JCLR #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000101010pppppp1s0bbbbb dsp_ea_imm5_abs16 + JCLR #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
|
||||
- C_DSPIM C_DD NOPARMO %00001010110001dd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_DDD NOPARMO %0000101011001ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_TTT NOPARMO %0000101011010ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_NNN NOPARMO %0000101011011ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_FFF NOPARMO %0000101011100ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
- C_DSPIM C_GGG NOPARMO %0000101011101ddd000bbbbb dsp_reg_imm5_abs16 JCLR #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
|
||||
lua M_DSPEA C_LUADST NOPARMO %00000100010mmrrr0001dddd dsp_ea_lua mmrrr=ea (subset), dddd=(bit 3=(0=Rn, 1=Nn), bits 2-0=0-7)
|
||||
norm M_DSPR M_ACC56 NOPARMO %0000000111011rrr0001d101 dsp_ab_rn norm Rn,D D=(a=0, b=1)
|
||||
move M_AM_NONE M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm00000000 dsp_self
|
||||
movec M_DSPIM8 C_MOVEC NOPARMO %00000101iiiiiiii101ddddd dsp_immmovec + move(c) #xx,d1
|
||||
- M_DSPEA C_MOVEC NOPARMO %0000010111mmmrrr0s1ddddd dsp_movec_ea + move(c) x:ea,d1 / y:ea,d1
|
||||
- C_MOVEC M_DSPEA NOPARMO %0000010101mmmrrr0s1ddddd dsp_movec_ea + move(c) s1,x:ea / s1,y:ea
|
||||
- C_DSPIM C_MOVEC NOPARMO %0000010111110100001ddddd dsp_movec_ea + move(c) #xxxx,d1
|
||||
- M_DSPAA C_MOVEC NOPARMO %0000010110aaaaaa0s1ddddd dsp_movec_aa + move(c) x:aa,d1 / y:aa,d1
|
||||
- C_MOVEC M_DSPAA NOPARMO %0000010100aaaaaa0s1ddddd dsp_movec_aa + move(c) s1,x:aa / s1,y:aa
|
||||
- C_MOVEC M_ALU24 NOPARMO %0000010001000eee101ddddd dsp_movec_reg + move(c) s1,d2
|
||||
- C_MOVEC C_DDD NOPARMO %0000010001001eee101ddddd dsp_movec_reg + move(c) s1,d2
|
||||
- C_MOVEC C_TTT NOPARMO %0000010001010eee101ddddd dsp_movec_reg + move(c) s1,d2
|
||||
- C_MOVEC C_NNN NOPARMO %0000010001011eee101ddddd dsp_movec_reg + move(c) s1,d2
|
||||
- C_MOVEC C_FFF NOPARMO %0000010001100eee101ddddd dsp_movec_reg + move(c) s1,d2
|
||||
- C_MOVEC C_GGG NOPARMO %0000010001111eee101ddddd dsp_movec_reg + move(c) s1,d2
|
||||
- M_ALU24 C_MOVEC NOPARMO %0000010011000eee101ddddd dsp_movec_reg + move(c) s2,d1
|
||||
- C_DDD C_MOVEC NOPARMO %0000010011001eee101ddddd dsp_movec_reg + move(c) s2,d1
|
||||
- C_TTT C_MOVEC NOPARMO %0000010011010eee101ddddd dsp_movec_reg + move(c) s2,d1
|
||||
- C_NNN C_MOVEC NOPARMO %0000010011011eee101ddddd dsp_movec_reg + move(c) s2,d1
|
||||
- C_FFF C_MOVEC NOPARMO %0000010011100eee101ddddd dsp_movec_reg + move(c) s2,d1
|
||||
- C_GGG C_MOVEC NOPARMO %0000010011111eee101ddddd dsp_movec_reg move(c) s2,d1
|
||||
movem M_ALU24 M_DSPEA NOPARMO %0000011101mmmrrr10000ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- C_DDD M_DSPEA NOPARMO %0000011101mmmrrr10001ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- C_TTT M_DSPEA NOPARMO %0000011101mmmrrr10010ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- C_NNN M_DSPEA NOPARMO %0000011101mmmrrr10011ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- C_FFF M_DSPEA NOPARMO %0000011101mmmrrr10100ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- C_GGG M_DSPEA NOPARMO %0000011101mmmrrr10111ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- M_DSPEA M_ALU24 NOPARMO %0000011111mmmrrr10000ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- M_DSPEA C_DDD NOPARMO %0000011111mmmrrr10001ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- M_DSPEA C_TTT NOPARMO %0000011111mmmrrr10010ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- M_DSPEA C_NNN NOPARMO %0000011111mmmrrr10011ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- M_DSPEA C_FFF NOPARMO %0000011111mmmrrr10100ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- M_DSPEA C_GGG NOPARMO %0000011111mmmrrr10111ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
|
||||
- M_ALU24 M_DSPAA NOPARMO %0000011100aaaaaa00000ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- C_DDD M_DSPAA NOPARMO %0000011100aaaaaa00001ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- C_TTT M_DSPAA NOPARMO %0000011100aaaaaa00010ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- C_NNN M_DSPAA NOPARMO %0000011100aaaaaa00011ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- C_FFF M_DSPAA NOPARMO %0000011100aaaaaa00100ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- C_GGG M_DSPAA NOPARMO %0000011100aaaaaa00111ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- M_DSPAA M_ALU24 NOPARMO %0000011110aaaaaa00000ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- M_DSPAA C_DDD NOPARMO %0000011110aaaaaa00001ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- M_DSPAA C_TTT NOPARMO %0000011110aaaaaa00010ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- M_DSPAA C_NNN NOPARMO %0000011110aaaaaa00011ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- M_DSPAA C_FFF NOPARMO %0000011110aaaaaa00100ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
|
||||
- M_DSPAA C_GGG NOPARMO %0000011110aaaaaa00111ddd dsp_movem_aa move(m) s,p:aa / p:aa,d
|
||||
mac M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk10 dsp_mult mac -+s1,s2,d / mac -+s2,s1,d
|
||||
macr M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk11 dsp_mult macr -+s1,s2,d / macr -+s2,s1,d
|
||||
mpy M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk00 dsp_mult mpy -+s1,d2,d / -+s2,s1,d
|
||||
mpyr M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk01 dsp_mult mpyr -+s1,d2,d / -+s2,s1,d
|
||||
movep M_DSPEA M_DSPPP NOPARMO %0000100s11mmmrrr1spppppp dsp_movep_ea + movep p:ea,x:pp / p:ea,y:pp
|
||||
- M_DSPAA M_DSPPP NOPARMO %0000100s11mmmrrr1spppppp dsp_movep_ea + movep p:aa,x:pp / p:aa,y:pp
|
||||
- M_DSPPP M_DSPEA NOPARMO %0000100s01mmmrrr1spppppp dsp_movep_ea + x:pp,p:ea / y:pp,p:ea
|
||||
- M_DSPPP M_DSPPP NOPARMO %0000100s01mmmrrr1spppppp dsp_movep_ea + x:pp,p:ea / y:pp,p:ea
|
||||
- M_DSPPP M_DSPAA NOPARMO %0000100s01mmmrrr1spppppp dsp_movep_ea + x:pp,p:aa / y:pp,p:aa
|
||||
- C_DSPIM M_DSPPP NOPARMO %0000100s111101001spppppp dsp_movep_ea + #xxxxxx,x:pp / #xxxxxx,y:pp
|
||||
- C_DSPIM M_DSPEA NOPARMO %0000100s111101001spppppp dsp_movep_ea + #xxxxxx,x:pp / #xxxxxx,y:pp
|
||||
- M_ALU24 M_DSPPP NOPARMO %0000100s11000ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
|
||||
- C_DDD M_DSPPP NOPARMO %0000100s11001ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
|
||||
- C_TTT M_DSPPP NOPARMO %0000100s11010ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
|
||||
- C_NNN M_DSPPP NOPARMO %0000100s11011ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
|
||||
- C_FFF M_DSPPP NOPARMO %0000100s11100ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
|
||||
- C_GGG M_DSPPP NOPARMO %0000100s11111ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
|
||||
- M_DSPPP M_ALU24 NOPARMO %0000100s01000ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
|
||||
- M_DSPPP C_DDD NOPARMO %0000100s01001ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
|
||||
- M_DSPPP C_TTT NOPARMO %0000100s01010ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
|
||||
- M_DSPPP C_NNN NOPARMO %0000100s01011ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
|
||||
- M_DSPPP C_FFF NOPARMO %0000100s01100ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
|
||||
- M_DSPPP C_GGG NOPARMO %0000100s01111ddd0spppppp dsp_movep_reg movep x:pp,d / y:pp,d
|
||||
debug M_AM_NONE M_AM_NONE NOPARMO %000000000000001000000000 dsp_self
|
||||
debugcc M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000000 dsp_self
|
||||
debughs M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000000 dsp_self
|
||||
debugcs M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001000 dsp_self
|
||||
debuglo M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001000 dsp_self
|
||||
debugec M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000101 dsp_self
|
||||
debugeq M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001010 dsp_self
|
||||
debuges M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001101 dsp_self
|
||||
debugge M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000001 dsp_self
|
||||
debuggt M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000111 dsp_self
|
||||
debuglc M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000110 dsp_self
|
||||
debugle M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001111 dsp_self
|
||||
debugls M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001110 dsp_self
|
||||
debuglt M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001001 dsp_self
|
||||
debugmi M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001011 dsp_self
|
||||
debugne M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000010 dsp_self
|
||||
debugnr M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001100 dsp_self
|
||||
debugpl M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000011 dsp_self
|
||||
debugnn M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000100 dsp_self
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,149 @@
|
|||
//
|
||||
// RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System
|
||||
// DSP56K_AMODE.H - Addressing Modes for Motorola DSP56001
|
||||
// Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends
|
||||
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
|
||||
// Source utilised with the kind permission of Landon Dyer
|
||||
//
|
||||
|
||||
#ifndef __DSP56K_AMODE_H__
|
||||
#define __DSP56K_AMODE_H__
|
||||
|
||||
#include "rmac.h"
|
||||
#include "amode.h"
|
||||
|
||||
// Addressing-mode masks
|
||||
|
||||
#define M_ACC56 0x00000001L // Accumulators A=A2:A1:A0 and B=B2:B1:B0
|
||||
#define M_ACC48 0x00000002L // Accumulators AB=A1:B1, BA=B1:A1, A10=A1:A0, B10=B1:B0
|
||||
#define M_ACC24 0x00000004L // Accumulators A0, A1, B0 and B1
|
||||
#define M_ACC8 0x00000008L // Accumulators A2 and B2
|
||||
#define M_INP48 0x00000010L // Input registers X=X1:X0 and Y=Y1:Y0
|
||||
#define M_ALU24 0x00000020L // Data ALU input registers X1, X0, Y1, Y0
|
||||
#define M_DSPIM 0x00000040L // #data
|
||||
#define M_DSPIM12 0x00000080L // #data
|
||||
//#define M_DSPIM24 0x0000010 // #data
|
||||
#define M_DSPPCU 0x00000200L // Program control unit registers PC, MR, CCR, SR, OMR, LA, LC, SP, SS, SSH, SSL
|
||||
#define M_DSPEA 0x00000400L // Effective addressing modes (Rn)-Nn, (Rn)+Nn, (Rn)-, (Rn)+, (Rn), (Rn+Nn), -(Rn), <absolute address>
|
||||
#define M_DSPAA 0x00000800L // 6-bit Absolute Short Address
|
||||
#define M_DSPPP 0x00001000L // 6-bit I/O Short Address
|
||||
#define M_DSPM 0x00002000L // Modifier registers M0-M7
|
||||
#define M_DSPR 0x00004000L // Address registers R0-R7
|
||||
#define M_DSPN 0x00008000L // Address offset registers N0-N7
|
||||
#define M_DSPABS12 0x00010000L // xxx.12bit
|
||||
#define M_DSPABS24 0x00020000L // xxx.24bit
|
||||
#define M_DSPABS06 0x00040000L // xxx.6bit
|
||||
#define M_DSPABS16 0x00080000L // xxx.16bit
|
||||
#define M_DSPIM8 0x00100000L // #data
|
||||
|
||||
#define M_ALL48 (M_ACC56|M_INP48|M_ALU24) // Input registers X=X1:X0, Y=Y1:Y0, A=A2:A1:A0, B=B2:B1:B0, X0, X1, Y0, Y1
|
||||
|
||||
#define C_DD (M_ALU24) // 4 registers in data ALU: x0, x1, y0, y1
|
||||
#define C_DDD (M_ACC56|M_ACC24|M_ACC8) // 8 accumulators in data ALU: a0, b0, a2, b2, a1, b1, a, b
|
||||
#define C_LLL (M_ACC56|M_ACC48|M_INP48) // 8 extended-precision registers in data ALU: a10, b10, x, y, a, b, ab, ba
|
||||
#define C_FFF (M_DSPM) // 8 address modifier registers in address ALU: m0-m7
|
||||
#define C_NNN (M_DSPN) // 8 address offset registers in address ALU: n0-n7
|
||||
#define C_TTT (M_DSPR) // 8 address registers in address: r0-r7
|
||||
#define C_GGG (M_DSPPCU) // 8 program controller registers: sr, omr, sp, ssh, la, lc
|
||||
#define C_A18 (M_ALU24|C_DDD|C_LLL|C_FFF|C_NNN|C_TTT|C_GGG) // All of the above registers
|
||||
|
||||
#define C_DSPABS24 (M_DSPABS06|M_DSPABS12|M_DSPABS16|M_DSPABS24) // Everything up to 24-bit addresses
|
||||
#define C_DSPABSEA (C_DSPABS24|M_DSPEA) // All absolute addresses and all other ea addressing modes
|
||||
#define C_DSPABS16 (M_DSPABS06|M_DSPABS12|M_DSPABS16) // Everything up to 16-bit addresses
|
||||
#define C_LUADST (M_DSPR|M_DSPN) // Mask for LUA instruction destination
|
||||
#define C_MOVEC (M_DSPM|M_DSPPCU) // M0-M7 and SR, OMR, LA, LC, SP, SS, SSH, SSL
|
||||
#define C_DSPIM (M_DSPIM8 | M_DSPIM | M_DSPIM12) // All the immmediate sizes we want to alias
|
||||
|
||||
// Xn Input Register X1 or X0 (24 Bits)
|
||||
// Yn Input Register Y1 or Y0 (24 Bits)
|
||||
// An Accumulator Registers A2, A1, A0 (A2 — 8 Bits, A1 and A0 — 24 Bits)
|
||||
// Bn Accumulator Registers B2, B1, B0 (B2 — 8 Bits, B1 and B0 — 24 Bits)
|
||||
// X Input Register X = X1: X0 (48 Bits)
|
||||
// Y Input Register Y = Y1: Y0 (48 Bits)
|
||||
// A Accumulator A = A2: A1: A0 (56 Bits)*
|
||||
// B Accumulator B = B2: B1: B0 (56 BIts)*
|
||||
// AB Accumulators A and B = A1: B1 (48 Bits)*
|
||||
// BA Accumulators B and A = B1: A1 (48 Bits)*
|
||||
// A10 Accumulator A = A1: A0 (48 Bits)
|
||||
// B10 Accumulator B= B1:B0 (48 bits)
|
||||
|
||||
// Attribute masks
|
||||
#define PARMOVE 0x00000001L
|
||||
#define NOPARMO 0x00000000L
|
||||
|
||||
// DSP EA modes
|
||||
|
||||
#define DSP_EA_POSTDEC B8(00000000)
|
||||
#define DSP_EA_POSTINC B8(00001000)
|
||||
#define DSP_EA_POSTDEC1 B8(00010000)
|
||||
#define DSP_EA_POSTINC1 B8(00011000)
|
||||
#define DSP_EA_NOUPD B8(00100000)
|
||||
#define DSP_EA_INDEX B8(00101000)
|
||||
#define DSP_EA_PREDEC1 B8(00111000)
|
||||
#define DSP_EA_ABS B8(00110000)
|
||||
#define DSP_EA_IMM B8(00110100)
|
||||
|
||||
|
||||
// Mnemonic table structure
|
||||
#define MNTABDSP struct _mntabdsp
|
||||
MNTABDSP {
|
||||
LONG mn0, mn1; // Addressing modes
|
||||
WORD mnattr; // Attributes (PARMOVE, ...)
|
||||
LONG mninst; // Instruction mask
|
||||
WORD mncont; // Continuation (or -1)
|
||||
int (* mnfunc)(LONG); // Mnemonic builder
|
||||
};
|
||||
|
||||
// Addressing mode variables, output of dsp_amode()
|
||||
int dsp_am0; // Addressing mode
|
||||
int dsp_a0reg; // Register
|
||||
int dsp_am1; // Addressing mode
|
||||
int dsp_a1reg; // Register
|
||||
int dsp_am2; // Addressing mode
|
||||
int dsp_a2reg; // Register
|
||||
int dsp_am3; // Addressing mode
|
||||
int dsp_a3reg; // Register
|
||||
|
||||
TOKEN dsp_a0expr[EXPRSIZE]; // Expression
|
||||
uint64_t dsp_a0exval; // Expression's value
|
||||
WORD dsp_a0exattr; // Expression's attribute
|
||||
SYM * dsp_a0esym; // External symbol involved in expr
|
||||
LONG dsp_a0memspace; // Addressing mode's memory space (P, X, Y)
|
||||
LONG dsp_a0perspace; // Peripheral space (X, Y - used in movep)
|
||||
TOKEN dsp_a1expr[EXPRSIZE]; // Expression
|
||||
uint64_t dsp_a1exval; // Expression's value
|
||||
WORD dsp_a1exattr; // Expression's attribute
|
||||
SYM * dsp_a1esym; // External symbol involved in expr
|
||||
LONG dsp_a1memspace; // Addressing mode's memory space (P, X, Y)
|
||||
LONG dsp_a1perspace; // Peripheral space (X, Y - used in movep)
|
||||
TOKEN dsp_a2expr[EXPRSIZE]; // Expression
|
||||
uint64_t dsp_a2exval; // Expression's value
|
||||
WORD dsp_a2exattr; // Expression's attribute
|
||||
SYM * dsp_a2esym; // External symbol involved in expr
|
||||
TOKEN dsp_a3expr[EXPRSIZE]; // Expression
|
||||
uint64_t dsp_a3exval; // Expression's value
|
||||
WORD dsp_a3exattr; // Expression's attribute
|
||||
SYM * dsp_a3esym; // External symbol involved in expr
|
||||
int dsp_k; // Multiplications sign
|
||||
TOKEN dspImmedEXPR[EXPRSIZE]; // Expression
|
||||
uint64_t dspImmedEXVAL; // Expression's value
|
||||
WORD dspImmedEXATTR; // Expression's attribute
|
||||
SYM * dspImmedESYM; // External symbol involved in expr
|
||||
int deposit_extra_ea; // Optional effective address extension
|
||||
|
||||
|
||||
// Extra ea deposit modes
|
||||
enum
|
||||
{
|
||||
DEPOSIT_EXTRA_WORD = 1,
|
||||
DEPOSIT_EXTRA_FIXUP = 2,
|
||||
};
|
||||
|
||||
|
||||
// Prototypes
|
||||
int dsp_amode(int maxea);
|
||||
LONG parmoves(WORD dest);
|
||||
int dsp_tcc4(LONG inst);
|
||||
|
||||
#endif // __DSP56K_AMODE_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,24 @@
|
|||
//
|
||||
// RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System
|
||||
// DSP56L_MACH.C - Code Generation for Motorola DSP56001
|
||||
// Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends
|
||||
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
|
||||
// Source utilised with the kind permission of Landon Dyer
|
||||
//
|
||||
|
||||
#ifndef __DSP56KMACH_H__
|
||||
#define __DSP56KMACH_H__
|
||||
|
||||
#include "rmac.h"
|
||||
#include "dsp56k_amode.h"
|
||||
|
||||
// Exported variables
|
||||
extern MNTABDSP dsp56k_machtab[];
|
||||
extern unsigned int dsp_orgaddr;
|
||||
extern unsigned int dsp_orgseg;
|
||||
|
||||
// Exported functions
|
||||
extern int dsp_mult(LONG inst);
|
||||
|
||||
#endif // __DSP56KMACH_H__
|
||||
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
//
|
||||
// RMAC - Reboot's Macro Assembler for all Atari computers
|
||||
// 68KGEN.C - Tool to Generate 68000 Opcode Table
|
||||
// Copyright (C) 199x Landon Dyer, 2011-2018 Reboot and Friends
|
||||
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
|
||||
// Source utilised with the kind permission of Landon Dyer
|
||||
//
|
||||
|
||||
#include <stdio.h>
|
||||
#include <ctype.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
|
||||
#define EOS '\0'
|
||||
|
||||
int kwnum = 1; /* current op# for kwgen output */
|
||||
FILE * kfp; /* keyword file */
|
||||
int lineno = 0;
|
||||
|
||||
// Function prototypes
|
||||
void error(char *, char *);
|
||||
void procln(int, char **);
|
||||
|
||||
|
||||
int main(int argc, char ** argv)
|
||||
{
|
||||
char * namv[256];
|
||||
char * s;
|
||||
int namcnt;
|
||||
char ln[256];
|
||||
|
||||
if ((argc == 2) && ((kfp = fopen(argv[1], "w")) == NULL))
|
||||
error("Cannot create: %s", argv[1]);
|
||||
|
||||
while (fgets(ln, 256, stdin) != NULL)
|
||||
{
|
||||
lineno++; /* bump line# */
|
||||
|
||||
if (*ln == '#') /* ignore comments */
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Tokenize line (like the way "argc, argv" works)
|
||||
* and pass it to the parser.
|
||||
*/
|
||||
namcnt = 0;
|
||||
s = ln;
|
||||
|
||||
while (*s)
|
||||
{
|
||||
if (isspace(*s))
|
||||
++s;
|
||||
else
|
||||
{
|
||||
namv[namcnt++] = s;
|
||||
|
||||
while (*s && !isspace(*s))
|
||||
s++;
|
||||
|
||||
if (isspace(*s))
|
||||
*s++ = EOS;
|
||||
}
|
||||
}
|
||||
|
||||
if (namcnt)
|
||||
procln(namcnt, namv);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Parse line
|
||||
//
|
||||
void procln(int namc, char ** namv)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
// alias for previous entry
|
||||
if (namc == 1)
|
||||
{
|
||||
fprintf(kfp, "%s\t%d\n", namv[0], kwnum - 1 + 2000);
|
||||
return;
|
||||
}
|
||||
|
||||
if (namc < 5)
|
||||
{
|
||||
fprintf(stderr, "%d: missing fields\n", lineno);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
// output keyword name
|
||||
if (*namv[0] != '-')
|
||||
fprintf(kfp, "%s\t%d\n", namv[0], kwnum + 2000);
|
||||
|
||||
printf("/*%4d %-6s*/ {", kwnum, namv[0]);
|
||||
|
||||
printf("%s, %s, %s, ", namv[1], namv[2], namv[3]);
|
||||
|
||||
// enforce little fascist percent signs
|
||||
if (*namv[4] == '%')
|
||||
{
|
||||
for(i=1, j=0; i<25; i++)
|
||||
{
|
||||
j <<= 1;
|
||||
|
||||
if (namv[4][i] == '1' || isupper(namv[4][i]))
|
||||
j++;
|
||||
}
|
||||
|
||||
printf("0x%06x, ", j);
|
||||
}
|
||||
else
|
||||
printf("%s, ", namv[4]);
|
||||
|
||||
if (namc >= 7 && *namv[6] == '+')
|
||||
printf("%d, ", kwnum + 1);
|
||||
else
|
||||
printf("0, ");
|
||||
|
||||
printf("%s},\n", namv[5]);
|
||||
|
||||
kwnum++;
|
||||
}
|
||||
|
||||
|
||||
void error(char * s, char * s1)
|
||||
{
|
||||
fprintf(stderr, s, s1);
|
||||
fprintf(stderr, "\n");
|
||||
exit(1);
|
||||
}
|
||||
|
||||
65
expr.c
65
expr.c
|
|
@ -36,7 +36,7 @@ char itokcl[] = {
|
|||
CR_STREQ, CR_MACDEF,
|
||||
CR_DATE, CR_TIME,
|
||||
CR_ABSCOUNT, 0,
|
||||
'!', '~', UNMINUS, 0, // UNARY
|
||||
'!', '~', UNMINUS, UNLT, UNGT, 0, // UNARY
|
||||
'*', '/', '%', 0, // MULT
|
||||
'+', '-', 0, // ADD
|
||||
SHL, SHR, 0, // SHIFT
|
||||
|
|
@ -49,6 +49,7 @@ char itokcl[] = {
|
|||
|
||||
const char missym_error[] = "missing symbol";
|
||||
const char str_error[] = "missing symbol or string";
|
||||
const char noflt_error[] = "operator not usable with float";
|
||||
|
||||
// Convert expression to postfix
|
||||
static PTR evalTokenBuffer; // Deposit tokens here (this is really a
|
||||
|
|
@ -125,23 +126,24 @@ int expr0(void)
|
|||
//
|
||||
int expr1(void)
|
||||
{
|
||||
TOKEN t;
|
||||
SYM * sy;
|
||||
char * p, * p2;
|
||||
char * p;
|
||||
WORD w;
|
||||
int j;
|
||||
|
||||
int class = tokenClass[*tok];
|
||||
|
||||
if (*tok == '-' || *tok == '+' || class == UNARY)
|
||||
if (*tok == '-' || *tok == '+' || *tok == '<' || *tok == '>' || class == UNARY)
|
||||
{
|
||||
t = *tok++;
|
||||
TOKEN t = *tok++;
|
||||
|
||||
if (expr2() != OK)
|
||||
return ERROR;
|
||||
|
||||
if (t == '-')
|
||||
t = UNMINUS;
|
||||
else if (t == '<')
|
||||
t = UNLT;
|
||||
else if (t == '>')
|
||||
t = UNGT;
|
||||
|
||||
// With leading + we don't have to deposit anything to the buffer
|
||||
// because there's no unary '+' nor we have to do anything about it
|
||||
|
|
@ -183,8 +185,9 @@ getsym:
|
|||
return error(missym_error);
|
||||
|
||||
p = string[*tok++];
|
||||
j = (*p == '.' ? curenv : 0);
|
||||
w = ((sy = lookup(p, LABEL, j)) != NULL && (sy->sattr & w) ? 1 : 0);
|
||||
int j = (*p == '.' ? curenv : 0);
|
||||
SYM * sy = lookup(p, LABEL, j);
|
||||
w = ((sy != NULL) && (sy->sattr & w ? 1 : 0));
|
||||
*evalTokenBuffer.u32++ = CONST;
|
||||
*evalTokenBuffer.u64++ = (uint64_t)w;
|
||||
break;
|
||||
|
|
@ -201,7 +204,7 @@ getsym:
|
|||
if (*tok != SYMBOL && *tok != STRING)
|
||||
return error(str_error);
|
||||
|
||||
p2 = string[tok[1]];
|
||||
char * p2 = string[tok[1]];
|
||||
tok += 2;
|
||||
|
||||
w = (WORD)(!strcmp(p, p2));
|
||||
|
|
@ -222,9 +225,6 @@ getsym:
|
|||
//
|
||||
int expr2(void)
|
||||
{
|
||||
char * p;
|
||||
SYM * sy;
|
||||
int j;
|
||||
PTR ptk;
|
||||
|
||||
switch (*tok++)
|
||||
|
|
@ -242,9 +242,10 @@ int expr2(void)
|
|||
tok = ptk.u32;
|
||||
break;
|
||||
case SYMBOL:
|
||||
p = string[*tok++];
|
||||
j = (*p == '.' ? curenv : 0);
|
||||
sy = lookup(p, LABEL, j);
|
||||
{
|
||||
char * p = string[*tok++];
|
||||
int j = (*p == '.' ? curenv : 0);
|
||||
SYM * sy = lookup(p, LABEL, j);
|
||||
|
||||
if (sy == NULL)
|
||||
sy = NewSymbol(p, LABEL, j);
|
||||
|
|
@ -264,6 +265,7 @@ int expr2(void)
|
|||
symbolPtr[symbolNum] = sy;
|
||||
symbolNum++;
|
||||
break;
|
||||
}
|
||||
case STRING:
|
||||
*evalTokenBuffer.u32++ = CONST;
|
||||
*evalTokenBuffer.u64++ = str_value(string[*tok++]);
|
||||
|
|
@ -494,10 +496,15 @@ thrown away right here. What the hell is it for?
|
|||
|
||||
tok += 2;
|
||||
}
|
||||
// Holy hell... This is likely due to the fact that LSR is mistakenly set as a SUNARY type... Need to fix this... !!! FIX !!!
|
||||
else if (m6502)
|
||||
{
|
||||
*evalTokenBuffer.u32++ = *tok++;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Unknown type here... Alert the user!,
|
||||
error("undefined RISC register in expression");
|
||||
error("undefined RISC register in expression [token=$%X]", *tok);
|
||||
// Prevent spurious error reporting...
|
||||
tok++;
|
||||
return ERROR;
|
||||
|
|
@ -691,6 +698,30 @@ printf("EVEXPR (-): sym1 = %X, sym2 = %X\n", attr, sattr[1]);
|
|||
|
||||
break;
|
||||
|
||||
case UNLT: // Unary < (get the low byte of a word)
|
||||
//printf("evexpr(): UNLT\n");
|
||||
if (*sattr & TDB)
|
||||
return error(seg_error);
|
||||
|
||||
if (*sattr & FLOAT)
|
||||
return error(noflt_error);
|
||||
|
||||
*sval = (int64_t)((*sval) & 0x00FF);
|
||||
*sattr = ABS | DEFINED; // Expr becomes absolute
|
||||
break;
|
||||
|
||||
case UNGT: // Unary > (get the high byte of a word)
|
||||
//printf("evexpr(): UNGT\n");
|
||||
if (*sattr & TDB)
|
||||
return error(seg_error);
|
||||
|
||||
if (*sattr & FLOAT)
|
||||
return error(noflt_error);
|
||||
|
||||
*sval = (int64_t)(((*sval) >> 8) & 0x00FF);
|
||||
*sattr = ABS | DEFINED; // Expr becomes absolute
|
||||
break;
|
||||
|
||||
case '!':
|
||||
//printf("evexpr(): !\n");
|
||||
if (*sattr & TDB)
|
||||
|
|
|
|||
|
|
@ -68,13 +68,6 @@ fp4 228
|
|||
fp5 229
|
||||
fp6 230
|
||||
fp7 231
|
||||
mr 272
|
||||
omr 273
|
||||
la 274
|
||||
lc 275
|
||||
ssh 276
|
||||
ssl 277
|
||||
ss 278
|
||||
|
||||
.equ 61
|
||||
equ 61
|
||||
|
|
@ -128,4 +121,46 @@ time 120
|
|||
date 121
|
||||
abscount 122
|
||||
|
||||
x0 260
|
||||
x1 261
|
||||
y0 262
|
||||
y1 263
|
||||
b0 265
|
||||
b2 267
|
||||
b1 269
|
||||
a 270
|
||||
b 271
|
||||
n0 280
|
||||
n1 281
|
||||
n2 282
|
||||
n3 283
|
||||
n4 284
|
||||
n5 285
|
||||
n6 286
|
||||
n7 287
|
||||
m0 288
|
||||
m1 289
|
||||
m2 290
|
||||
m3 291
|
||||
m4 292
|
||||
m5 293
|
||||
m6 294
|
||||
m7 295
|
||||
|
||||
mr 304
|
||||
omr 305
|
||||
la 306
|
||||
lc 307
|
||||
ssh 308
|
||||
ssl 309
|
||||
ss 310
|
||||
|
||||
l 302
|
||||
p 303
|
||||
|
||||
a10 312
|
||||
b10 313
|
||||
x 314
|
||||
y 315
|
||||
ab 318
|
||||
ba 319
|
||||
154
makefile
154
makefile
|
|
@ -1,6 +1,6 @@
|
|||
#
|
||||
# RMAC - Reboot's Macro Assembler for the Atari Jaguar
|
||||
# Copyright (C) 199x Landon Dyer, 2011 Reboot & Friends
|
||||
# RMAC - Reboot's Macro Assembler for all Atari computers
|
||||
# Copyright (C) 199x Landon Dyer, 2011-2018 Reboot & Friends
|
||||
# MAKEFILE for *nix
|
||||
#
|
||||
|
||||
|
|
@ -20,22 +20,21 @@ STD := gnu99
|
|||
endif
|
||||
|
||||
|
||||
rm = /bin/rm -f
|
||||
RM = /bin/rm -f
|
||||
CC = $(CROSS)gcc
|
||||
HOSTCC = gcc
|
||||
|
||||
#CFLAGS = -std=$(STD) -D_DEFAULT_SOURCE -g -D__GCCUNIX__ -I. -O2 -MMD
|
||||
CFLAGS = -std=$(STD) -D_DEFAULT_SOURCE -g -D__GCCUNIX__ -I. -O2
|
||||
|
||||
SRCS = 6502.c amode.c debug.c direct.c eagen.c error.c expr.c fltpoint.c listing.c mach.c macro.c mark.c object.c op.c procln.c riscasm.c rmac.c sect.c symbol.c token.c
|
||||
|
||||
OBJS = 6502.o amode.o debug.o direct.o eagen.o error.o expr.o fltpoint.o listing.o mach.o macro.o mark.o object.o op.o procln.o riscasm.o rmac.o sect.o symbol.o token.o
|
||||
OBJS = 6502.o amode.o debug.o direct.o dsp56k.o dsp56k_amode.o dsp56k_mach.o eagen.o error.o expr.o fltpoint.o listing.o mach.o macro.o mark.o object.o op.o procln.o riscasm.o rmac.o sect.o symbol.o token.o
|
||||
|
||||
#
|
||||
# Build everything
|
||||
#
|
||||
|
||||
all : mntab.h 68ktab.h kwtab.h risckw.h 6502kw.h opkw.h rmac
|
||||
#all: mntab.h 68ktab.h kwtab.h risckw.h 6502kw.h opkw.h dsp56ktab.h rmac
|
||||
all: rmac
|
||||
@echo
|
||||
@echo "Don't forget to bump the version number before commiting!"
|
||||
@echo
|
||||
|
|
@ -45,106 +44,48 @@ all : mntab.h 68ktab.h kwtab.h risckw.h 6502kw.h opkw.h rmac
|
|||
# definitions
|
||||
#
|
||||
|
||||
mntab.h : mntab 68kmn kwgen
|
||||
cat mntab 68kmn | ./kwgen mn >mntab.h
|
||||
68ktab.h 68k.tab: 68k.mch 68kgen
|
||||
./68kgen 68k.tab <68k.mch >68ktab.h
|
||||
|
||||
68ktab.h 68kmn : 68ktab 68ktab 68kgen
|
||||
./68kgen 68kmn <68ktab >68ktab.h
|
||||
dsp56ktab.h dsp56k.tab: dsp56k.mch dsp56kgen
|
||||
./dsp56kgen dsp56k.tab <dsp56k.mch >dsp56ktab.h
|
||||
|
||||
|
||||
kwtab.h : kwtab kwgen
|
||||
./kwgen kw <kwtab >kwtab.h
|
||||
mntab.h: direct.tab 68k.tab kwgen
|
||||
cat direct.tab 68k.tab | ./kwgen mn >mntab.h
|
||||
|
||||
6502kw.h : 6502.tbl kwgen
|
||||
./kwgen mp <6502.tbl >6502kw.h
|
||||
kwtab.h: kw.tab kwgen
|
||||
./kwgen kw <kw.tab >kwtab.h
|
||||
|
||||
risckw.h : kwtab kwgen
|
||||
./kwgen mr <risctab >risckw.h
|
||||
6502kw.h: 6502.tab kwgen
|
||||
./kwgen mp <6502.tab >6502kw.h
|
||||
|
||||
opkw.h : op.tab kwgen
|
||||
risckw.h: risc.tab kwgen
|
||||
./kwgen mr <risc.tab >risckw.h
|
||||
|
||||
opkw.h: op.tab kwgen
|
||||
./kwgen mo <op.tab >opkw.h
|
||||
|
||||
# Looks like this is not needed...
|
||||
dsp56kkw.h: dsp56k.tab kwgen
|
||||
./kwgen dsp <dsp56k.tab >dsp56kkw.h
|
||||
|
||||
#
|
||||
# Build tools
|
||||
#
|
||||
|
||||
kwgen.o : kwgen.c
|
||||
$(HOSTCC) $(CFLAGS) -c kwgen.c
|
||||
|
||||
kwgen : kwgen.o
|
||||
$(HOSTCC) $(CFLAGS) -o kwgen kwgen.o
|
||||
|
||||
68kgen.o : 68kgen.c
|
||||
$(HOSTCC) $(CFLAGS) -c 68kgen.c
|
||||
|
||||
68kgen : 68kgen.o
|
||||
$(HOSTCC) $(CFLAGS) -o 68kgen 68kgen.o
|
||||
%gen: %gen.c
|
||||
$(HOSTCC) $(CFLAGS) -c $<
|
||||
$(HOSTCC) $(CFLAGS) -o $*gen $<
|
||||
|
||||
#
|
||||
# Build RMAC executable
|
||||
#
|
||||
|
||||
6502.o : 6502.c 6502.h
|
||||
$(CC) $(CFLAGS) -c 6502.c
|
||||
%.o: %.c %.h
|
||||
$(CC) $(CFLAGS) -c $<
|
||||
|
||||
amode.o : amode.c amode.h
|
||||
$(CC) $(CFLAGS) -c amode.c
|
||||
|
||||
debug.o : debug.c debug.h
|
||||
$(CC) $(CFLAGS) -c debug.c
|
||||
|
||||
direct.o : direct.c direct.h
|
||||
$(CC) $(CFLAGS) -c direct.c
|
||||
|
||||
eagen.o : eagen.c eagen.h eagen0.c
|
||||
$(CC) $(CFLAGS) -c eagen.c
|
||||
|
||||
error.o : error.c error.h
|
||||
$(CC) $(CFLAGS) -c error.c
|
||||
|
||||
expr.o : expr.c expr.h
|
||||
$(CC) $(CFLAGS) -c expr.c
|
||||
|
||||
fltpoint.o : fltpoint.c fltpoint.h
|
||||
$(CC) $(CFLAGS) -c fltpoint.c
|
||||
|
||||
listing.o : listing.c listing.h
|
||||
$(CC) $(CFLAGS) -c listing.c
|
||||
|
||||
mach.o : mach.c mach.h
|
||||
$(CC) $(CFLAGS) -c mach.c
|
||||
|
||||
macro.o : macro.c macro.h
|
||||
$(CC) $(CFLAGS) -c macro.c
|
||||
|
||||
mark.o : mark.c mark.h
|
||||
$(CC) $(CFLAGS) -c mark.c
|
||||
|
||||
object.o : object.c object.h
|
||||
$(CC) $(CFLAGS) -c object.c
|
||||
|
||||
op.o : op.c op.h
|
||||
$(CC) $(CFLAGS) -c op.c
|
||||
|
||||
procln.o : procln.c procln.h
|
||||
$(CC) $(CFLAGS) -c procln.c
|
||||
|
||||
riscasm.o : riscasm.c riscasm.h
|
||||
$(CC) $(CFLAGS) -c riscasm.c
|
||||
|
||||
rmac.o : rmac.c rmac.h
|
||||
$(CC) $(CFLAGS) -c rmac.c
|
||||
|
||||
sect.o : sect.c sect.h
|
||||
$(CC) $(CFLAGS) -c sect.c
|
||||
|
||||
symbol.o : symbol.c symbol.h
|
||||
$(CC) $(CFLAGS) -c symbol.c
|
||||
|
||||
token.o : token.c token.h
|
||||
$(CC) $(CFLAGS) -c token.c
|
||||
|
||||
rmac : $(OBJS)
|
||||
rmac: $(OBJS)
|
||||
$(CC) $(CFLAGS) -o rmac $(OBJS) -lm
|
||||
|
||||
#
|
||||
|
|
@ -152,30 +93,37 @@ rmac : $(OBJS)
|
|||
#
|
||||
|
||||
clean:
|
||||
$(rm) $(OBJS) kwgen.o 68kgen.o rmac kwgen 68kgen kwtab.h 68ktab.h mntab.h risckw.h 6502kw.h opkw.h
|
||||
$(RM) $(OBJS) kwgen.o 68kgen.o rmac kwgen 68kgen 68k.tab kwtab.h 68ktab.h mntab.h risckw.h 6502kw.h opkw.h dsp56kgen dsp56kgen.o dsp56k.tab dsp56kkw.h dsp56ktab.h
|
||||
|
||||
#
|
||||
# Dependencies
|
||||
#
|
||||
6502.o: 6502.c direct.h rmac.h symbol.h token.h expr.h error.h mach.h \
|
||||
procln.h riscasm.h sect.h
|
||||
68kgen.o: 68kgen.c
|
||||
procln.h riscasm.h sect.h kwtab.h
|
||||
68kgen: 68kgen.c
|
||||
amode.o: amode.c amode.h rmac.h symbol.h error.h expr.h mach.h procln.h \
|
||||
token.h sect.h kwtab.h mntab.h parmode.h
|
||||
token.h sect.h riscasm.h kwtab.h mntab.h parmode.h
|
||||
debug.o: debug.c debug.h rmac.h symbol.h amode.h direct.h token.h expr.h \
|
||||
mark.h sect.h
|
||||
mark.h sect.h riscasm.h
|
||||
direct.o: direct.c direct.h rmac.h symbol.h token.h 6502.h amode.h \
|
||||
error.h expr.h fltpoint.h listing.h mach.h macro.h mark.h procln.h \
|
||||
riscasm.h sect.h kwtab.h
|
||||
dsp56k.o: dsp56k.c rmac.h symbol.h dsp56k.h sect.h riscasm.h
|
||||
dsp56k_amode.o: dsp56k_amode.c dsp56k_amode.h rmac.h symbol.h amode.h \
|
||||
error.h token.h expr.h procln.h sect.h riscasm.h kwtab.h mntab.h
|
||||
dsp56k_mach.o: dsp56k_mach.c dsp56k_mach.h rmac.h symbol.h dsp56k_amode.h \
|
||||
amode.h direct.h token.h dsp56k.h sect.h riscasm.h error.h kwtab.h \
|
||||
dsp56ktab.h
|
||||
dsp56kgen: dsp56kgen.c
|
||||
eagen.o: eagen.c eagen.h rmac.h symbol.h amode.h error.h fltpoint.h \
|
||||
mach.h mark.h riscasm.h sect.h token.h eagen0.c
|
||||
error.o: error.c error.h rmac.h symbol.h listing.h token.h
|
||||
expr.o: expr.c expr.h rmac.h symbol.h direct.h token.h error.h listing.h \
|
||||
mach.h procln.h riscasm.h sect.h kwtab.h
|
||||
fltpoint.o: fltpoint.c fltpoint.h
|
||||
kwgen.o: kwgen.c
|
||||
kwgen: kwgen.c
|
||||
listing.o: listing.c listing.h rmac.h symbol.h error.h procln.h token.h \
|
||||
sect.h version.h
|
||||
sect.h riscasm.h version.h
|
||||
mach.o: mach.c mach.h rmac.h symbol.h amode.h direct.h token.h eagen.h \
|
||||
error.h expr.h procln.h riscasm.h sect.h kwtab.h 68ktab.h
|
||||
macro.o: macro.c macro.h rmac.h symbol.h debug.h direct.h token.h error.h \
|
||||
|
|
@ -183,20 +131,20 @@ macro.o: macro.c macro.h rmac.h symbol.h debug.h direct.h token.h error.h \
|
|||
mark.o: mark.c mark.h rmac.h symbol.h error.h object.h riscasm.h sect.h
|
||||
object.o: object.c object.h rmac.h symbol.h 6502.h direct.h token.h \
|
||||
error.h mark.h riscasm.h sect.h
|
||||
op.o: op.c op.h rmac.h symbol.h direct.h token.h error.h expr.h \
|
||||
fltpoint.h mark.h procln.h riscasm.h sect.h
|
||||
op.o: op.c op.h direct.h rmac.h symbol.h token.h error.h expr.h \
|
||||
fltpoint.h mark.h procln.h riscasm.h sect.h opkw.h
|
||||
procln.o: procln.c procln.h rmac.h symbol.h token.h 6502.h amode.h \
|
||||
direct.h error.h expr.h listing.h mach.h macro.h op.h riscasm.h sect.h \
|
||||
kwtab.h mntab.h risckw.h 6502kw.h opkw.h
|
||||
direct.h dsp56kkw.h error.h expr.h listing.h mach.h macro.h op.h riscasm.h \
|
||||
sect.h kwtab.h mntab.h risckw.h 6502kw.h opkw.h
|
||||
riscasm.o: riscasm.c riscasm.h rmac.h symbol.h amode.h direct.h token.h \
|
||||
error.h expr.h mark.h procln.h sect.h risckw.h kwtab.h
|
||||
rmac.o: rmac.c rmac.h symbol.h 6502.h debug.h direct.h token.h error.h \
|
||||
expr.h listing.h mark.h macro.h object.h procln.h riscasm.h sect.h \
|
||||
version.h
|
||||
sect.o: sect.c sect.h rmac.h symbol.h 6502.h direct.h token.h error.h \
|
||||
expr.h listing.h mach.h mark.h riscasm.h
|
||||
sect.o: sect.c sect.h rmac.h symbol.h riscasm.h 6502.h direct.h token.h \
|
||||
error.h expr.h listing.h mach.h mark.h
|
||||
symbol.o: symbol.c symbol.h error.h rmac.h listing.h object.h procln.h \
|
||||
token.h
|
||||
token.o: token.c token.h rmac.h symbol.h direct.h error.h macro.h \
|
||||
procln.h sect.h kwtab.h
|
||||
procln.h sect.h riscasm.h kwtab.h
|
||||
|
||||
|
|
|
|||
107
procln.c
107
procln.c
|
|
@ -10,6 +10,8 @@
|
|||
#include "6502.h"
|
||||
#include "amode.h"
|
||||
#include "direct.h"
|
||||
#include "dsp56k_amode.h"
|
||||
#include "dsp56k_mach.h"
|
||||
#include "error.h"
|
||||
#include "expr.h"
|
||||
#include "listing.h"
|
||||
|
|
@ -39,6 +41,11 @@
|
|||
#define DECL_MO // Include OP keyword state machine tables
|
||||
#include "opkw.h"
|
||||
|
||||
#define DEF_DSP // Include DSP56K keywords definitions
|
||||
#define DECL_DSP // Include DSP56K keyword state machine tables
|
||||
#include "dsp56kkw.h"
|
||||
|
||||
|
||||
IFENT * ifent; // Current ifent
|
||||
static IFENT ifent0; // Root ifent
|
||||
IFENT * f_ifent; // Freelist of ifents
|
||||
|
|
@ -696,6 +703,93 @@ When checking to see if it's already been equated, issue a warning.
|
|||
}
|
||||
}
|
||||
|
||||
// If we are in 56K mode and still in need of a mnemonic then search for one
|
||||
if (dsp56001 && ((state < 0) || (state >= 1000)))
|
||||
{
|
||||
for(state=0, p=opname; state>=0;)
|
||||
{
|
||||
j = dspbase[state] + (int)tolowertab[*p];
|
||||
|
||||
// Reject, character doesn't match
|
||||
if (dspcheck[j] != state)
|
||||
{
|
||||
state = -1; // No match
|
||||
break;
|
||||
}
|
||||
|
||||
// Must accept or reject at EOS
|
||||
if (!*++p)
|
||||
{
|
||||
state = dspaccept[j]; // (-1 on no terminal match)
|
||||
break;
|
||||
}
|
||||
|
||||
state = dsptab[j];
|
||||
}
|
||||
|
||||
// Call DSP code generator if we found a mnemonic
|
||||
if (state >= 2000)
|
||||
{
|
||||
LONG parcode;
|
||||
int operands;
|
||||
MNTABDSP * md = &dsp56k_machtab[state - 2000];
|
||||
deposit_extra_ea = 0; // Assume no extra word needed
|
||||
|
||||
if (md->mnfunc == dsp_mult)
|
||||
{
|
||||
// Special case for multiplication instructions: they require
|
||||
// 3 operands
|
||||
if ((operands = dsp_amode(3)) == ERROR)
|
||||
goto loop;
|
||||
}
|
||||
else if ((md->mnattr & PARMOVE) && md->mn0 != M_AM_NONE)
|
||||
{
|
||||
if (dsp_amode(2) == ERROR)
|
||||
goto loop;
|
||||
}
|
||||
else if ((md->mnattr & PARMOVE) && md->mn0 == M_AM_NONE)
|
||||
{
|
||||
// Instructions that have parallel moves but use no operands
|
||||
// (probably only move). In this case, don't parse addressing
|
||||
// modes--just go straight to parallel parse
|
||||
dsp_am0 = dsp_am1 = M_AM_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Non parallel move instructions can have up to 4 parameters
|
||||
// (well, only tcc instructions really)
|
||||
if ((operands = dsp_amode(4)) == ERROR)
|
||||
goto loop;
|
||||
|
||||
if (operands == 4)
|
||||
{
|
||||
dsp_tcc4(md->mninst);
|
||||
goto loop;
|
||||
}
|
||||
}
|
||||
|
||||
if (md->mnattr & PARMOVE)
|
||||
{
|
||||
// Check for parallel moves
|
||||
if ((parcode = parmoves(dsp_a1reg)) == ERROR)
|
||||
goto loop;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (*tok != EOL)
|
||||
error("parallel moves not allowed with this instruction");
|
||||
|
||||
parcode = 0;
|
||||
}
|
||||
|
||||
while ((dsp_am0 & md->mn0) == 0 || (dsp_am1 & md->mn1) == 0)
|
||||
md = &dsp56k_machtab[md->mncont];
|
||||
|
||||
(*md->mnfunc)(md->mninst | (parcode << 8));
|
||||
goto loop;
|
||||
}
|
||||
}
|
||||
|
||||
// Invoke macro or complain about bad mnemonic
|
||||
if (state < 0)
|
||||
{
|
||||
|
|
@ -760,16 +854,11 @@ When checking to see if it's already been equated, issue a warning.
|
|||
// Keep a backup of chptr (used for optimisations during codegen)
|
||||
chptr_opcode = chptr;
|
||||
|
||||
for(;;)
|
||||
{
|
||||
if ((m->mnattr & siz) && (amsk0 & m->mn0) != 0 && (amsk1 & m->mn1) != 0)
|
||||
{
|
||||
(*m->mnfunc)(m->mninst, siz);
|
||||
goto loop;
|
||||
}
|
||||
|
||||
while ((m->mnattr & siz) && (amsk0 & m->mn0) == 0 || (amsk1 & m->mn1) == 0)
|
||||
m = &machtab[m->mncont];
|
||||
}
|
||||
|
||||
(*m->mnfunc)(m->mninst, siz);
|
||||
goto loop;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
5
rmac.h
5
rmac.h
|
|
@ -219,7 +219,12 @@ PTR
|
|||
#define DATA 0x0002 // Relative to data
|
||||
#define BSS 0x0004 // Relative to BSS
|
||||
#define M6502 0x0008 // 6502/microprocessor (absolute)
|
||||
#define M56001P 0x0010 // DSP 56001 Program RAM
|
||||
#define M56001X 0x0020 // DSP 56001 X RAM
|
||||
#define M56001Y 0x0040 // DSP 56001 Y RAM
|
||||
#define M56001L 0x0080 // DSP 56001 L RAM
|
||||
#define TDB (TEXT|DATA|BSS) // Mask for text+data+bss
|
||||
#define M56KPXYL (M56001P|M56001X|M56001Y|M56001L) // Mask for 56K stuff
|
||||
|
||||
// Sizes
|
||||
#define SIZB 0x0001 // .b
|
||||
|
|
|
|||
37
sect.c
37
sect.c
|
|
@ -91,12 +91,12 @@ void InitSection(void)
|
|||
//
|
||||
void MakeSection(int sno, uint16_t attr)
|
||||
{
|
||||
SECT * p = §[sno];
|
||||
p->scattr = attr;
|
||||
p->sloc = 0;
|
||||
p->orgaddr = 0;
|
||||
p->scode = p->sfcode = NULL;
|
||||
p->sfix = p->sffix = NULL;
|
||||
SECT * sp = §[sno];
|
||||
sp->scattr = attr;
|
||||
sp->sloc = 0;
|
||||
sp->orgaddr = 0;
|
||||
sp->scode = sp->sfcode = NULL;
|
||||
sp->sfix = sp->sffix = NULL;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -108,15 +108,15 @@ void SwitchSection(int sno)
|
|||
{
|
||||
CHUNK * cp;
|
||||
cursect = sno;
|
||||
SECT * p = §[sno];
|
||||
SECT * sp = §[sno];
|
||||
|
||||
m6502 = (sno == M6502); // Set 6502-mode flag
|
||||
|
||||
// Copy section vars
|
||||
scattr = p->scattr;
|
||||
sloc = p->sloc;
|
||||
scode = p->scode;
|
||||
orgaddr = p->orgaddr;
|
||||
scattr = sp->scattr;
|
||||
sloc = sp->sloc;
|
||||
scode = sp->scode;
|
||||
orgaddr = sp->orgaddr;
|
||||
|
||||
// Copy code chunk vars
|
||||
if ((cp = scode) != NULL)
|
||||
|
|
@ -126,6 +126,12 @@ void SwitchSection(int sno)
|
|||
chptr = cp->chptr + ch_size;
|
||||
|
||||
// For 6502 mode, add the last org'd address
|
||||
// Why?
|
||||
/*
|
||||
Because the way this is set up it treats the 6502 assembly space as a single 64K space (+ 16 bytes, for some reason) and just bobbles around inside that space and uses a stack of org "pointers" to show where the data ended up.
|
||||
|
||||
This is a piss poor way to handle things, and for fucks sake, we can do better than this!
|
||||
*/
|
||||
if (m6502)
|
||||
chptr = cp->chptr + orgaddr;
|
||||
}
|
||||
|
|
@ -139,11 +145,11 @@ void SwitchSection(int sno)
|
|||
//
|
||||
void SaveSection(void)
|
||||
{
|
||||
SECT * p = §[cursect];
|
||||
SECT * sp = §[cursect];
|
||||
|
||||
p->scattr = scattr; // Bailout section vars
|
||||
p->sloc = sloc;
|
||||
p->orgaddr = orgaddr;
|
||||
sp->scattr = scattr; // Bailout section vars
|
||||
sp->sloc = sloc;
|
||||
sp->orgaddr = orgaddr;
|
||||
|
||||
if (scode != NULL) // Bailout code chunk
|
||||
scode->ch_size = ch_size;
|
||||
|
|
@ -711,7 +717,6 @@ int ResolveFixups(int sno)
|
|||
if (fup->orgaddr)
|
||||
addr = fup->orgaddr;
|
||||
|
||||
|
||||
eval = (quad & 0xFFFFFC0000FFFFFFLL) | ((addr & 0x3FFFF8) << 21);
|
||||
}
|
||||
else if (w & FU_OBJDATA)
|
||||
|
|
|
|||
31
sect.h
31
sect.h
|
|
@ -10,6 +10,7 @@
|
|||
#define __SECT_H__
|
||||
|
||||
#include "rmac.h"
|
||||
#include "riscasm.h"
|
||||
|
||||
// Macros to deposit code in the current section (in Big Endian)
|
||||
#define D_byte(b) {chcheck(1);*chptr++=(uint8_t)(b); sloc++; ch_size++; \
|
||||
|
|
@ -38,7 +39,7 @@
|
|||
sloc+=2; ch_size+=2;if(orgactive) orgaddr += 2;}
|
||||
|
||||
// Macro for the 56001. Word size on this device is 24 bits wide. I hope that
|
||||
// orgaddr += 1 means that the addresses in the device reflect this.
|
||||
// orgaddr += 1 means that the addresses in the device reflect this. [A: Yes.]
|
||||
#define D_dsp(w) {chcheck(3);*chptr++=(uint8_t)(w>>16); \
|
||||
*chptr++=(uint8_t)(w>>8); *chptr++=(uint8_t)w; \
|
||||
sloc+=1; ch_size += 3; if(orgactive) orgaddr += 1; \
|
||||
|
|
@ -77,6 +78,8 @@
|
|||
#define FU_BYTEH 0x0008 // Fixup 6502 high byte of immediate word
|
||||
#define FU_BYTEL 0x0009 // Fixup 6502 low byte of immediate word
|
||||
#define FU_QUAD 0x000A // Fixup quad-word (8 bytes)
|
||||
#define FU_56001 0x000B // Generic fixup code for all 56001 modes
|
||||
#define FU_56001_B 0x000C // Generic fixup code for all 56001 modes (ggn: I have no shame)
|
||||
|
||||
#define FU_SEXT 0x0010 // Ok to sign extend
|
||||
#define FU_PCREL 0x0020 // Subtract PC first
|
||||
|
|
@ -99,14 +102,34 @@
|
|||
#define FU_DONE 0x8000 // Fixup has been done
|
||||
|
||||
// FPU fixups
|
||||
#define FU_FLOATSING 0x000B // Fixup 32-bit float
|
||||
#define FU_FLOATDOUB 0x000C // Fixup 64-bit float
|
||||
#define FU_FLOATEXT 0x000D // Fixup 96-bit float
|
||||
#define FU_FLOATSING 0x000D // Fixup 32-bit float
|
||||
#define FU_FLOATDOUB 0x000E // Fixup 64-bit float
|
||||
#define FU_FLOATEXT 0x000F // Fixup 96-bit float
|
||||
|
||||
// OP fixups
|
||||
#define FU_OBJLINK 0x10000 // Fixup OL link addr (bits 24-42, drop last 3)
|
||||
#define FU_OBJDATA 0x20000 // Fixup OL data addr (bits 43-63, drop last 3)
|
||||
|
||||
// DSP56001 fixups
|
||||
// TODO: Sadly we don't have any spare bits left inside a 16-bit word
|
||||
// so we use the 2nd nibble as control code and
|
||||
// stick $B or $C in the lower nibble - then it's picked up as
|
||||
// FU_56001 by the fixup routine and then a second switch
|
||||
// selects fixup mode. Since we now have 32 bits, we can fix this!
|
||||
// [N.B.: This isn't true anymore, we now have 32 bits! :-P]
|
||||
#define FU_DSPIMM5 0x090B // Fixup 5-bit immediate
|
||||
#define FU_DSPADR12 0x0A0B // Fixup 12-bit address
|
||||
#define FU_DSPADR24 0x0B0B // Fixup 24-bit address
|
||||
#define FU_DSPADR16 0x0C0B // Fixup 24-bit address
|
||||
#define FU_DSPIMM12 0x0D0B // Fixup 12-bit immediate
|
||||
#define FU_DSPIMM24 0x0E0B // Fixup 24-bit immediate
|
||||
#define FU_DSPIMM8 0x0F0B // Fixup 8-bit immediate
|
||||
#define FU_DSPADR06 0x090C // Fixup 6-bit address
|
||||
#define FU_DSPPP06 0x0A0C // Fixup 6 bit pp address
|
||||
#define FU_DSPIMMFL8 0x0B0C // Fixup 8-bit immediate float
|
||||
#define FU_DSPIMMFL16 0x0C0C // Fixup 16-bit immediate float
|
||||
#define FU_DSPIMMFL24 0x0D0C // Fixup 24-bit immediate float
|
||||
|
||||
|
||||
// Chunks are used to hold generated code and fixup records
|
||||
#define CHUNK struct _chunk
|
||||
|
|
|
|||
2
token.h
2
token.h
|
|
@ -63,6 +63,8 @@
|
|||
#define DOTQ 'Q' // .q or .Q (essentially an alias for P)
|
||||
#define DOTS 'S' // .s or .S (FPU Single)
|
||||
#define ENDEXPR 'E' // End of expression
|
||||
#define UNLT 0x81 // Unary '<' (low byte)
|
||||
#define UNGT 0x82 // Unary '>' (high byte)
|
||||
|
||||
// ^^ operators
|
||||
#define CR_DEFINED 'p' // ^^defined - is symbol defined?
|
||||
|
|
|
|||
Loading…
Reference in New Issue